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MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS81C7208 GMS81C7216
User's Manual (Ver. 1.04)
REVISION HISTORY
VERSION 1.04 (FEB. 2005) This book Fixed some errata at page32 (Port Mode Register). VERSION 1.03 (SEP. 2004) This book The company name, Hynix Semiconductor Inc. changed to MagnaChip Semiconductor Ltd. VERSION 1.02 (AUG. 2003) Delete IDD3 and the following sentence at page11. The bit7(SUBM) of LCR register must be set to "1" by software because of reduction current consumption(reset value="0"). VERSION 1.01 (AUG. 2003) Fixed some errata. VERSION 1.00 (AUG. 2003) First Edition 44MQFP/LQFP package.
Version 1.04 Published by MCU Application Team 2004 MagnaChip Semiconductor Ltd. All right reserved. Additional information of this manual may be served by MagnaChip Semiconductor offices in Korea or Distributors and Representatives listed at address directory. MagnaChip Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS81C7208/7216
1. OVERVIEW .........................................................1 Description .........................................................1 Features .............................................................1 Development Tools ............................................2 Ordering Information ..........................................2 2. BLOCK DIAGRAM .............................................3 3. PIN ASSIGNMENT .............................................4 4. PACKAGE DIMENSION .....................................5 5. PIN FUNCTION ...................................................6 6. PORT STRUCTURES 7 7. ELECTRICAL CHARACTERISTICS ................10 Absolute Maximum Ratings .............................10 Recommended Operating Conditions ..............10 DC Electrical Characteristics ...........................10 A/D Converter Characteristics .........................12 AC Characteristics ...........................................12 Serial Interface Timing Characteristics ............14 Typical Characteristics .....................................15 8. MEMORY ORGANIZATION .............................17 Registers ..........................................................17 Program Memory .............................................20 Data Memory ...................................................23 List of Control Registers ...................................24 Addressing Mode .............................................27 9. I/O PORTS ........................................................31 Port Data Registers ..........................................31 I/O Ports Configuration ....................................32 10. CLOCK GENERATOR ...................................36 11. OPERATION MODE .......................................38 Operation Mode ...............................................39 12. BASIC INTERVAL TIMER ..............................40 13. TIMER/EVENT COUNTER .............................42 8-bit Timer / Counter Mode ..............................45 16-bit Timer / Counter Mode ............................49 8-bit Capture Mode ..........................................50 16-bit Capture Mode ........................................51 14. ANALOG DIGITAL CONVERTER ..................52
15. SERIAL COMMUNICATION .......................... 54 Transmission/Receiving Timing ...................... 55 The Method of Serial I/O ................................. 56 The Method to Test Correct Transmission ...... 56 16. BUZZER FUNCTION ..................................... 57 17. INTERRUPTS ................................................ 59 Interrupt Sequence .......................................... 61 BRK Interrupt .................................................. 62 Multi Interrupt .................................................. 62 External Interrupt ............................................. 63 18. LCD DRIVER ................................................. 65 LCD Control Registers .................................... 66 Duty and Bias Selection of LCD Driver ........... 67 Selecting Frame Frequency ............................ 67 LCD Display Memory ...................................... 70 Control Method of LCD Driver ......................... 71 19. WATCH / WATCHDOG TIMER ..................... 73 Watch Timer .................................................... 73 Watchdog Timer .............................................. 73 20. POWER DOWN OPERATION ....................... 76 SLEEP Mode ................................................... 76 STOP Mode .................................................... 77 21. OSCILLATOR CIRCUIT ................................ 80 22. RESET ........................................................... 81 External Reset Input ........................................ 81 Watchdog Timer Reset ................................... 81 23. POWER FAIL PROCESSOR ......................... 82 24. DEVELOPMENT TOOLS ............................... 84 OTP Programming .......................................... 84 Emulator EVA. Board Setting .......................... 86 A. MASK ORDER SHEET ..................................... ii B. INSTRUCTION ................................................. iii Terminology List ................................................ iii Instruction Map ..................................................iv Instruction Set ....................................................v C. SOFTWARE EXAMPLE ................................. xiii
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GMS81C7208/16
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH LCD DRIVER & A/D CONVERTER
1. OVERVIEW
1.1 Description
The GMS81C7208/7216 is advanced CMOS 8-bit microcontrollers with 8K/16K bytes of ROM. There are a powerful microcontroller which provides a highly flexible and cost effective solution to many LCD applications. These provide the following standard features:8K/ 16K bytes of mask type ROM or 16K bytes OTP ROM, 448 bytes of RAM, 8-bit Timer/Counter, 8-bit A/D converter, programmable buzzer driving port, 8-bit basic interval timer, watch dog timer, serial peripheral interface, on chip oscillator and clock circuitry. They also come with 4com/17seg LCD driver. In addition, it support power saving mode to reduce power consumption. Device Name GMS81C7208 GMS81C7216 ROM Size 8K bytes 16K bytes RAM Size 448 bytes 448 bytes I/O 29 29 OTP GMS87C7216 Package 44MQFP, 44LQFP
1.2 Features
* 8K/16K Bytes On-chip Programmable ROM * 448 Bytes of On-chip Data RAM (Included Stack Area and 27 Nibbles LCD Display RAM) * Minimum Instruction Execution Time 1s at 4MHz (2cycle NOP Instruction) * One 8-bit Basic Interval Timer * One Watch Timer * One Watchdog Timer * Four 8-bit Timer/Event Counter (or Two 16-bit Timer/Event Counter) * Three External Interrupt Input Ports * One Programmable 6-bit Buzzer Driving Port - 500Hz ~ 250kHz@4MHz * 29 I/O Ports * Three Channel 8-bit A/D Converter * One 8-bit Serial Communication Interface * LCD Display/ Controller - Static Mode (20SEG x 1COM, Static) - 1/2 Duty Mode (19SEG x 2COM, 1/2 or 1/3 Bias) - 1/3 Duty Mode (18SEG x 3COM, 1/3 Bias) - 1/4 Duty Mode (17SEG x 4COM, 1/3 Bias) - Internal Built-in Resistor Circuit for Bias * Twelve Interrupt Sources - Basic Interval Timer: 1 - External Input: 3 - Timer/Event Counter: 4 - ADC: 1 - Serial Interface: 1 - WT:1 - WDT: 1 * Main Clock Oscillation (1.0~4.5MHz) - Crystal - Ceramic Resonator - External R Oscillator (Built-in Capacitor) * Power Saving Operation Mode - 2/8/16/64 Divided System Clock Selectable * Power Down Mode - STOP Mode - SLEEP Mode * Wide Temperature Range - Industrial : -40C ~ + 85C * 2.7V to 5.5V Wide Operating Voltage Range * Noise Immunity Circuit for EMS - Power Fail Processor - Built-in Noise Filter * 44MQFP, 44LQFP Package Types * Available 16K Bytes OTP Version
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1.3 Development Tools
Note: There are several setting switches in the Emulator. User should read carefully and do setting properly before developing the program refer to "24.2 Emulator EVA. Board Setting" on page 86. Otherwise, the Emulator may not work properly. Windows 95/98/2000/XPTM. Please contact sales part of MagnaChip Semiconductor.
Software Hardware (Emulator) OTP programmer
- MS- Window base assembler - Linker / Editor / Debugger - CHOICE-Dr. - CHOICE-Dr. EVA81C7X B/D - PGM-Plus - CHOICE-SIGMA (Single type) - CHOICE-GANG4 (4-gang type)
The GMS81C7208/16 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are two different type programmers, one is single type, another is gang type. For more detail, refer to OTP Programming chapter. Macro assembler operates under the MS-
1.4 Ordering Information
Device name GMS81C7208 Q GMS81C7216 Q GMS81C7208 LQ GMS81C7216 LQ GMS87C7216 Q GMS87C7216 LQ ROM Size (bytes) 8K bytes 16K bytes 8K bytes 16K bytes 16K bytes OTP 16K bytes OTP RAM size 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes 448 bytes Package 44MQFP 44MQFP 44LQFP 44LQFP 44MQFP 44LQFP
Mask ROM version
OTP ROM version
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2. BLOCK DIAGRAM
GMS81C7208/7216
Common Drive Output COM0 COM1/SEG26 COM2/SEG25 COM3/SEG24 LCD Power Supply VCL0 VCL1 VCL2 BIAS LCD Power Control Circuit
Segment Drive Output SEG0 ~ SEG11 SEG16 ~ SEG20
R40-R47 R50-R53 R60-R64
LCD Controller / Driver (LCDC)
R4
R5
R6
PSW
ALU
Accumulator
Stack Pointer
Data Memory LCD Display Memory
PC
Interrupt Controller RESET System controller System Clock Controller Timing generator XIN XOUT frequency Clock Generator
Watch/ Watchdog
Program Memory Data Table
8-bit Basic Interval Timer PC
Timer
8-bit A/D Converter
8-bit SIO Timer/Counter
VDD VSS AVDD AVSS Power Supply
Power Supply Circuit
R3
Buzzer Driver
R2
R0
R30 / BUZ
R21 / AN1 R22 / AN2 R23 / AN3
R00 / INT0 R01 / INT1 R02 / INT2 R03 / EC0 R04 / EC2 R05 / SCK R06 / SO R07 / SI
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3. PIN ASSIGNMENT
44MQFP (Top View)
4
AN2 / R22 AN3 / R23 AVSS BIAS XIN XOUT RESET VSS SI / R07 SO / R06 SCK / R05
1 2 3 4 5 6 7 8 9 10 11
SEG20 / R64 COM0 SEG26 / COM1 SEG25 / COM2 SEG24 / COM3 VDD VCL0 VCL1 VCL2 AVDD AN1 / R21
33 32 31 30 29 28 27 26 25 24 23
R63 / SEG19 R62 / SEG18 R61 / SEG17 R60 / SEG16 R53 / SEG11 R52 / SEG10 R51 / SEG9 R50 / SEG8 R47 / SEG7 R46 / SEG6 R45 / SEG5
44LQFP (Top View)
AN2 / R22 AN3 / R23 AVSS BIAS XIN XOUT RESET VSS SI / R07 SO / R06 SCK / R05
1 2 3 4 5 6 7 8 9 10 11
SEG20 / R64 COM0 SEG26 / COM1 SEG25 / COM2 SEG24 / COM3 VDD VCL0 VCL1 VCL2 AVDD AN1 / R21
33 32 31 30 29 28 27 26 25 24 23
R63 / SEG19 R62 / SEG18 R61 / SEG17 R60 / SEG16 R53 / SEG11 R52 / SEG10 R51 / SEG9 R50 / SEG8 R47 / SEG7 R46 / SEG6 R45 / SEG5
34 35 36 37 38 39 40 41 42 43 44
GMS81C7208/16
22 21 20 19 18 17 16 15 14 13 12
R44 / SEG4 R43 / SEG3 R42 / SEG2 R41 / SEG1 R40 / SEG0 R30 / BUZO R00 / INT0 R01 / INT1 R02 / INT2 R03 / EC0 R04 / EC2
34 35 36 37 38 39 40 41 42 43 44
GMS81C7208/16
22 21 20 19 18 17 16 15 14 13 12
R44 / SEG4 R43 / SEG3 R42 / SEG2 R41 / SEG1 R40 / SEG0 R30 / BUZO R00 / INT0 R01 / INT1 R02 / INT2 R03 / EC0 R04 / EC2
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4. PACKAGE DIMENSION
44MQFP
13.45 12.95 10.10 9.90
UNIT: MM
13.45 12.95 10.10 9.90
2.10 1.95
0-7 SEE DETAIL "A" 0.25 0.10 1.03 0.73 1.60 BSC DETAIL "A"
2.35 max. 0.45 0.30 0.80 BSC
44LQFP
12.20 11.80 10.10 9.90
UNIT: MM
12.20 11.80 10.10 9.90
1.45 1.35
0-7 SEE DETAIL "A" 0.15 0.05 0.75 0.45 1.00 BSC DETAIL "A"
1.60 max. 0.45 0.30 0.80 BSC
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0.23 0.13
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5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. AVSS: ADC circuit ground. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. BIAS: LCD bias voltage input pin. VCL0~VCL2: LCD driver power supply pins. The voltage on each pin is VCL2> VCL1> VCL0. For details, Refer to "18. LCD DRIVER" on page 65. COM0~COM3: LCD common signal output pins. Also, the pins of COM1,COM2 and COM3 are shared with LCD segment signal outputs of SEG26, SEG25, SEG24 as application requirement. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or schmitt trigger inputs. Also, pull-up resistors and open-drain outputs are software assignable. In addition, R0 serves the functions of the various following special features. Port Pin R00 R01 R02 R03 R04 R05 R06 R07 Alternate Function INT0 (External Interrupt 0) INT1 (External Interrupt 1) INT2 (External Interrupt 2) EC0 (Event Counter Input 0) EC2 (Event Counter Input 2) SCK (Serial Clock) SO (Serial Data Output) SI (Serial Data Input) written to the Port Direction Register can be used as output or input. Also, pull-up resistor and open-drain output is software assignable.
In addition, R30 serves the function of the following special feature.
Port Pin R30 Alternate Function BUZ (Buzzer driving output)
SEG0~SEG7: These pins generate LCD segment signal output. Every LCD segment pins are shared with normal R4 input/output port. R4 is an 8-bit CMOS bidirectional I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. LCD Pin Function SEG0 (LCD Segment 0 Signal Output) SEG1 (LCD Segment 1 Signal Output) SEG2 (LCD Segment 2 Signal Output) SEG3 (LCD Segment 3 Signal Output) SEG4 (LCD Segment 4 Signal Output) SEG5 (LCD Segment 5 Signal Output) SEG6 (LCD Segment 6 Signal Output) SEG7 (LCD Segment 7 Signal Output) Port Pin R40 R41 R42 R43 R44 R45 R46 R47
SEG8~SEG11: These pins generate LCD segment signal output. Every LCD segment pins are shared with normal R5 input/output port. R5 is an 4-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. LCD Pin Function SEG8 (LCD Segment 8 Signal Output) SEG9 (LCD Segment 9 Signal Output) SEG10 (LCD Segment 10 Signal Output) SEG11 (LCD Segment 11 Signal Output) Port Pin R50 R51 R52 R53
R21~R23: R2 is an 3-bit CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. Also, pull-up resistors and open-drain outputs are software assignable. In addition, R2 is shared with the ADC input. Port Pin R21 R22 R23 Alternate Function AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3)
SEG16~SEG20: These pins generate LCD segment signal output. Every LCD segment pins are shared with normal R6 input/output port. R6 is an 5-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. LCD Pin Function SEG16 (LCD Segment 16 Signal Output) SEG17 (LCD Segment 17 Signal Output) SEG18 (LCD Segment 18 Signal Output) SEG19 (LCD Segment 19 Signal Output) SEG20 (LCD Segment 20 Signal Output) Port Pin R60 R61 R62 R63 R64
R30: R3 is a 1-bit CMOS bidirectional I/O port. R30 pin 1 or 0
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6. PORT STRUCTURES
PIN NAME (Alternate) VDD VSS RESET AVDD AVSS XIN XOUT BIAS VCL0~VCL2 COM0 COM1(SEG26) COM2(SEG25) COM3(SEG24) R00 (INT0) R01 (INT1) R02 (INT2) R03 (EC0) R04 (EC2) R05 (SCK) R06 (SO) R07 (SI) R21~R23(AN1~AN3) R30(BUZO) SEG0 ~ SEG7 (R40~R47) SEG8 ~ SEG11 (R50~R53) SEG16 ~ SEG20 (R60~R64) In/Out (Alternate) I I O I I O O(O) O(O) O(O) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I/O) I/O (O) I/O (I) I/O(I) I/O(O) O (I/O) O (I/O) O (I/O) 3-bit General I/O Ports 1-bit General I/O Ports LCD Segment Signal Output LCD Segment Signal Output LCD Segment Signal Output 8-bit General I/O Ports External Interrupt 0 Input External Interrupt 1 Input External Interrupt 2 Input Timer/Counter 0 External Input Timer/Counter 1 External Input Serial Clock I/O Serial Data Output Serial Data Input Analog Voltage Input Buzzer Driving Output 8-bit General I/O Ports 4-bit General I/O Ports 5-bit General I/O Ports LCD Common Signal Output LCD Segment Signal output Supply Voltage Circuit Ground Reset Signal Input Supply Voltage Input Pin for ADC Ground Level Input Pin for ADC Oscillation Input Oscillation Output LCD Bias Voltage Input LCD Driver Power Supply LCD Common Signal Output Function Basic Alternate
Table 6-1 Port Function Description
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R00/INT0, R01/INT1, R02/INT2, R03/EC0, R04/EC2, R05/SCK, R07/SI
Pull up Reg. Open Drain Reg. Data Bus Data Reg. Pin VSS MUX RD Pull-up Tr.
RESET
VDD OTP MCU :disconnected Mask MCU :connected Noise Canceller OTP MCU :connected Mask MCU :disconnected VSS VDD High Voltage On(OTP) Enable OTP Program Mode Internal RESET
RESET VDD
Dir. Reg.
VSS INT0 ~ INT2 EC0,EC2 SI,SCK Noise Canceller Tr.: Transistor Reg.: Register
R30/BUZ, R06/SO
Pull up Reg. Open Drain Reg. Data Bus Data Reg. BUZ,SO Dir. Reg. VSS Pin VDD Pull-up Tr.
R40~R47, R50~R53, R60~R64 / SEG0~SEG11, SEG16~SEG20
VDD Data Bus Data Reg.
Dir. Reg. VSS MUX MUX RD RD
Pin
VCL2 LCD Data VCL2 Enable
R21/AN1~R23/AN3
Pull up Reg. Open Drain Reg. Data Bus Data Reg. Pin VSS MUX RD Pull-up Tr. LCD Data VCL1 Enable LCD Data VCL0 Enable VDD
VCL1
VCL0 LCD Data GND Enable VSS
Dir. Reg.
AN1 ~ AN3
Analog Switch
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COM0~COM3 / SEG26~SEG24
VCL2 LCD Data VCL2 Enable VCL1 LCD Data VCL1 Enable LCD Data VCL0 Enable VCL0 LCD Data GND Enable VSS Pin
XIN, XOUT
VDD
XIN
XOUT
VSS STOP & Main Clock OFF Main Clock
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of VSS pin ........................100 mA Maximum current into VDD pin ............................80 mA Maximum current sunk by (IOL per I/O Pin) ........20 mA Maximum output current sourced by (IOH per I/O Pin) ...............................................................................15 mA Maximum current (IOL) .................................... 100 mA Maximum current (IOH)...................................... 60 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Parameter Supply Voltage Operating Frequency Operating Temperature Symbol VDD fXIN TOPR Condition fXIN=4.19MHz VDD=2.7~5.5V Specifications Min. 2.7 1 -40 Max. 5.5 4.5 +85 Unit V MHz C
7.3 DC Electrical Characteristics
(TA=-40~85C, VDD=2.7~5.5V),
Parameter Symbol VIH1 VIH2 VIL1 VIL2 VOH1 VOH2 VOL1 VOL2 IIH1 IIH2 IIL1 IIL2 RPORT Condition RESET, R0 (except R06) Other pins RESET, R0 (except R06) Other pins R0,R2,R3 IOH1=-0.5mA SEG, COM IOH2=-30A R0,R2,R3 IOL1=0.4mA SEG, COM IOL2=30A VIN=VDD, All Input Pins except XIN VIN=VDD, XIN VIN=0, All Input Pins except XIN VIN=0, XIN VIN=0V, VDD=5.5V, R0, R2 Specifications Min. 0.8 VDD 0.7 VDD 0 0 VDD-0.1 VDD-0.2 60 Typ. 160 Max. VDD VDD 0.2 VDD 0.3 VDD 0.4 0.2 1 20 -1 -20 350 Unit V V V V V V V V A A A A k
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage Input High Leakage Current Input Low Leakage Current Pull-up Resistor
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Parameter LCD Voltage Dividing Resistor Voltage Drop |VDD-COMn| , n=0~3 Voltage Drop |VDD-SEGn| , n=0~26 VCL2 Output Voltage VCL1 Output Voltage VCL0 Output Voltage RC Oscillation Frequency
Symbol RLCD VDC VDS VCL2 VCL1 VCL0 fRC IDD1 VDD=5.5V
Condition
Specifications Min. 45 VDD-0.3 Typ. 65 VDD 0.66VDD 0.33VDD 2 2.9 (1.3) 0.4 (0.1) 1.0 (0.5) Max. 85 120 120 VDD+0.3 0.66VDD +0.3 0.33VDD +0.3 3 7.0 (3.0) 1.7 (1.0) 12 (5)
Unit k mV mV
VDD=2.7 ~ 5.5V -15A per Common Pin VDD=2.7 ~ 5.5V -15A per Segment Pin
VDD=2.7 ~ 5.5V, 1/3 Bias BIAS pin and VCL2 pin are shorted
0.66VDD -0.2 0.33VDD -0.3
V
R=60k, VDD= 5V Main Clock Operation Mode 2 VDD=5.5V10%, XIN=4MHz Sleep Mode 3 VDD=5.5V10%, XIN=4MHz Stop Mode 4 VDD=5V10%, XIN= 0Hz When the bit7 of LCR register is "1".
1 -
MHz mA mA A
Supply Current ( ) means at 3V operation
1
IDD2 IDD6
1. Supply current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator voltage divide resistor, LVD circuit and output port drive currents. 2. This mode set System Clock Mode Register(SCMR) to xxxx0000B that is fXIN/2 3. This mode set SCMR to xxxx0000B (fXIN/2) and set SMR to "1" 4. Main frequency clock stops and set SCMR to xxxx0011B and set SMR to "1".
** Caution : The bit7(SUBM) of LCR register must be set to "1" by software because of reduction current consumption (reset value ="0").
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7.4 A/D Converter Characteristics
(TA=25C, VSS=0V, VDD=5.0V, AVDD=5.0V @fXIN=4MHz)
Parameter Analog Input Voltage Range Non-linearity Error Differential Non-linearity Error Zero Offset Error Full Scale Error Gain Error Overall Accuracy AVDD Input Current Conversion Time Analog Power Supply Input Range Symbol VAIN NNLE NDNLE NZOE NFSE NGE NACC IREF TCONV AVDD VDD=5.0V VDD=3.0V VDD=AVDD=5.0V Test Condition Specifications Min. VSS-0.3 3.0 2.7 Typ.1 1.0 1.0 0.5 0.25 1.0 1.0 Max. AVDD+0.3 1.5 1.5 1.5 0.5 1.5 1.5 200 20 VDD Unit V LSB LSB LSB LSB LSB LSB A s V
1. Data in "Typ" column is at 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
7.5 AC Characteristics
(TA=-40~+85C, VDD=5V10%, VSS=0V)
Specifications Min. 0.455 80 2 8 2 Typ. Max. 4.2 20 20 -
Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Main oscillation Stabilizing Time Interrupt Pulse Width RESET Input Width Event Counter Input Pulse Width
Symbol fMAIN tMCPW tMRCP,tMFCP tMST tIW tRST tECW
Pins XIN XIN XIN XIN, XOUT at 4MHz INT0, INT1, INT2 RESET EC0, EC2
Unit MHz ns ns ms tSYS1 tSYS1 tSYS1
1. tSYS is one of 2/fMAIN or 8/fMAIN or 16/fMAIN or 64/fMAIN in the main clock operation mode.
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1/fMAIN
tMCPW
tMCPW VDD-0.5V
XIN
tSYS tMRCP tMFCP
0.5V
tIW
tIW
INT0, INT1 INT2
0.8VDD 0.2VDD
tRST
RESET
0.2VDD
tECW
tECW 0.8VDD 0.2VDD
EC0, EC2
Figure 7-1 Timing Chart
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7.6 Serial Interface Timing Characteristics
(TA=-40~+85C, VDD=2.7~5.5V, VSS=0V, fXIN=4MHz)
Parameter Serial Input Clock Pulse Serial Input Clock Pulse Width SIN Input Setup Time (External SCK) SIN Input Setup Time (Internal SCK) SIN Input Hold Time Serial Output Clock Cycle Time Serial Output Clock Pulse Width Serial Output Clock Pulse Transition Time Serial Output Delay Time
Symbol tSCYC tSCKW tSUS tSUS tHS tSCYC tSCKW tFSCK tRSCK sOUT
Pins SCK SCK SIN SIN SIN SCK SCK SCK SO
Specifications Min. 2tSYS+200 tSYS+70 100 200 tSYS+70 4tSYS tSYS-30 Typ. Max. 8 8 16tSYS 30 100
Unit ns ns ns ns ns ns ns ns ns
tFSCK 0.8VDD 0.2VDD
tSCKW
tSCYC tRSCK
tSCKW
SCLK
tSUS
tHS 0.8VDD 0.2VDD
SIN
tDS
SOUT
0.8VDD 0.2VDD
Figure 7-2 Serial I/O Timing Chart
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7.7 Typical Characteristics
This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation
IOH (mA) Ta=25C -8
IOH-VOH, VDD=3.0V
IOH (mA) -20
IOH-VOH, VDD=5.0V
Ta=25C R (k) 200
RPU-Ta, VDD=5.0V R0,R1,R2,R3 pin
-6
-15
-4
-10
100
-2 0 0.5 1.0 1.5 2.0 2.5 VOH (V)
-5 0 0 1 2 3 4 VOH 5 (V) -20 0 40 80 Ta (C)
IOL (mA) 20
IOL-VOL, VDD=3.0V
Ta=25C
I -VOL, IOL OL (mA) Ta=25C
40
VDD=5.5V
fXIN (MHz) 4
fXIN-VDD
Ta=25C R = 6.2k R = 20k R = 60k
15
30
3
10
20
2 1 0 2 3
5 VOL (V)
10 0 1 2 3 4 VOL 5 (V)
R = 180k VDD 6 (V)
0.5
1.0 1.5
2.0
2.5
4
5
VIH1 (V) 4 3 2 1 0
VDD-VIH1 R0 (except R06)
fXIN=4MHz Ta=25C
VIH2 (V) 4 3 2 1
VDD-VIH2 R2~R6 pin (include R06)
fXIN=4MHz Ta=25C
VDD-VIH3
VIH1 (V) 4 3 2 1 fXIN=4MHz Ta=25C
XIN
1
2
3
4
5
VDD 6 (V)
0 2 3 4 5
VDD 6 (V)
0 1 2 3 4 5
VDD 6 (V)
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VIH1 (V) 4 3 2 1 0
VDD-VIL1 R0 (except R06)
fXIN=4MHz Ta=25C
VIH2 (V) 4 3 2 1
VDD-VIL2 R2~R6 pin (include R06)
fXIN=4MHz Ta=25C
VDD-VIL3
VIH1 (V) 4 3 2 1 fXIN=4MHz Ta=25C
XIN
1
2
3
4
5
VDD 6 (V)
0 2 3 4 5
VDD 6 (V)
0 1 2 3 4 5
VDD 6 (V)
IDD (mA) 4 3 2 1 0
Normal Operation (Main opr.) IDD1-VDD
fXIN=4MHz Ta=25C IDD (A) 400 300 200 100 VDD 6 (V) 0
SLEEP Mode (Main opr.) ISLEEP(IDD2)-VDD
fXIN=4MHz Ta=25C
IDD (A) 4 3 2 1
STOP Mode ISTOP(IDD3)-VDD
fXIN=0Hz Ta=25C
2
3
4
5
2
3
4
5
VDD 6 (V)
0 2 3 4 5
VDD 6 (V)
IDD (A) 4 3 2 1 0
STOP Mode ISTOP(IDD6)-VDD
fSXIN=0Hz Ta=25C
2
3
4
5
VDD 6 (V)
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8. MEMORY ORGANIZATION
The GMS81C7208/16 has separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 8K/16K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area and the LCD display RAM area.
8.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Hardware Fixed SP (Stack Pointer) could be in 00H~FFH. LCD display RAM area is located in 100H~11AH, User must have concerning that Stack data does not cross over LCD RAM area.
cess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 011BH to 01FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used.
Bit 15 Stack Area (100H ~ 1FFH) 87 01H SP Bit 0 00H~FFH
Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y Y A Two 8-bit Registers can be used as a "YA" 16-bit Register A
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP
; SP FFH
Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be access (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in ex-
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result.
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PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when G=1, page is selected to "page 1" BRK FLAG
MSB NVGBH
I
Z
LSB C RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 3 OF ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by RPR register (address 0F3H). It is set by SETG inWhen content of RPR is above 2, malfunction will be occurred. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. struction and cleared by CLRG. RAM Page 0 page 0 page 1 page Reserved Reserved Instruction CLRG SETG SETG SETG SETG Bit1 of RPR X 0 0 1 1 Bit0 of RPR X 0 1 0 1
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At execution of a CALL/TCALL/PCALL Push down
At acceptance of interrupt
At execution of RET instruction
At execution of RET instruction
01FF 01FE 01FD 01FC
PCH PCL
01FF 01FE 01FD 01FC
PCH PCL PSW
Push down
01FF 01FE 01FD 01FC
PCH PCL
Pop up
01FF 01FE 01FE 01FC
PCH PCL PSW
Pop up
SP before execution SP after execution
01FF 01FD
01FF 01FC
01FD 01FF
01FC 01FF
At execution of PUSH instruction PUSH A (X,Y,PSW) 01FF 01FE 01FD 01FC A Push down
At execution of POP instruction POP A (X,Y,PSW) 01FF 01FE 01FD 01FC 01FFH A Pop up 0100H
Stack depth
SP before execution SP after execution
01FF 01FE
01FE 01FF
Figure 8-4 Stack Operation
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8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 8K/16K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6. As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program.
C000H
save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7. Example: Usage of TCALL The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
16K ROM
E000H
Address
0FFE0H E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE
Vector Area Memory Timer/Counter 3 Timer/Counter 2 Watch Timer A/D Converter Serial Peripheral Interface External Interrupt 2 Timer/Counter 1 Timer/Counter 0 External Interrupt 1 External Interrupt 0 Watchdog Timer Basic Interval Timer Key Scan RESET
GMS81C7208 8K ROM
FEFFH FF00H FFC0H TCALL area FFDFH FFE0H FFFFH Interrupt Vector Area PCALL area
GMS81C7216
Figure 8-5 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to
NOTE: "-" means reserved area.
Figure 8-6 Interrupt Vector Area
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Address 0FF00H
PCALL Area Memory
Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0.
PCALL Area (256 Bytes)
0FFFFH
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35 ~ ~
4A ~ ~ NEXT
01001010
1
FH FH
Reverse
~ ~
0FF00H 0FF35H NEXT
~ ~
0D125H
PC: 11111111 11010110 DH 6H
0FF00H 0FFD6H 0FFD7H 25 D1
3
2
0FFFFH
0FFFFH
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Example: The usage software example of Vector address for GMS81C7216. ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW 0FFE0H TIMER3 TIMER2 WATCH_TIMER ADC SIO NOT_USED NOT_USED INT2 TIMER1 TIMER0 INT1 INT0 WD_TIMER BIT_TIMER NOT_USED RESET ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Timer-3 Timer-2 Watch Timer ADC Serial Interface Int.2 Timer-1 Timer-0 Int.1 Int.0 Watchdog Timer Basic Interval Timer Reset
;
ORG ORG
0C000H 0E000H
; in case of 16K ROM Start address ; in case of 8K ROM Start address
;******************************************* ; MAIN PROGRAM * ;******************************************* ; RESET: LDM SCMR,#0 ;When main clock mode DI ;Disable All Interrupts LDM WDTR,#0 ;Disable Watch Dog Timer LDM RPR,#1 CLRG LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H ~ !00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR SETG LDX #0 RAM_CLR1: LDA #0 STA {X}+ CMPX #1BH ;DISPLAY RAM Clear(!0100H ~ !011AH) BNE RAM_CLR1 CLRG ; LDX #0FFH ;Stack Pointer Initialize TXSP ; LDM R0, #0 ;Normal Port 0 LDM R0DD,#82H ;Normal Port Direction LDM R0PU,#0 ;Normal Pull Up : : : LDM TDR0,#250 ;8us x 250 = 2000us LDM TM0,#0000_1111B ;Start Timer0, 8us at 4MHz LDM IRQH,#0 LDM IRQL,#0 LDM IENH,#0000_1110B ;Enable INT0, INT1, Timer0 LDM IENL,#0 LDM IEDS,#15H ;Select falling edge detect on INT pin LDM PMR,#3H ;Set external interrupt pin(INT0, INT1) EI ;Enable master interrupt
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8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and LCD memory.
0000H
Control Registers
The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the Timer/Counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction (SET1, CLR1). Do not use read-modify-write instruction. Use byte manipulation instruction, for example "LDM".
User Memory (192 Bytes)
PAGE0
00BFH 00C0H
Control Registers 00FFH 0100H LCD display RAM (27 Nibbles) 011AH 011BH User Memory or Stack Area (229 Bytes) PAGE1
Example; To write at CKCTLR
01FFH
LDM Figure 8-8 Data Memory Map
CKCTLR,#09H ;Divide ratio(/16)
User Memory
The both GMS81C7208/16 has 448 x 8 bits for the user memory (RAM). There are two page internal RAM. Page is selected by G-flag and RAM page selection register RPR. When G-flag is cleared to "0", always page 0 is selected regardless of RPR value. If G-flag is set to "1", page will be selected according to RPR value.
Stack Area
The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 19.
Page 0 G=0 RPR=1, G=1 Page 1 Page 0: 00~FFH Page 1: 100~1FFH
Figure 8-9 RAM Page Configuration
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8.4 List of Control Registers
Address 00C0 00C2 00C3 00C4 00C5 00C6 00C8 00CA 00CB 00CC 00CD 00CE 00D0 00D2 00D3 00D4 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00DF 00E0 00E1 00E2 00E3 00E4 00E6 Register Name R0 Port Data Register R2 Port Data Register R3 Port Data Register R4 Port Data Register R5 Port Data Register R6 Port Data Register R0 Port I/O Direction Register R2 Port I/O Direction Register R3 Port I/O Direction Register R4 Port I/O Direction Register R5 Port I/O Direction Register R6 Port I/O Direction Register R0 Port Pull-up Register R2 Port Pull-up Register R3 Port Pull-up Register R0 Port Open Drain Control Register R2 Port Open Drain Control Register R3 Port Open Drain Control Register Ext. Interrupt Edge Selection Register Port Mode Register Interrupt Enable Lower Byte Register Interrupt Enable Upper Byte Register Interrupt Request Flag Lower Byte Register Interrupt Request Flag Upper Byte Register Sleep Mode Register Watch Dog Timer Register Timer0 Mode Register Timer0 Counter Register Timer0 Data Register Timer0 Input Capture Register Timer1 Mode Register Timer1 Data Register Timer1 Counter Register Timer1 Input Capture Register Timer2 Mode Register Symbol R0 R2 R3 R4 R5 R6 R0DD R2DD R3DD R4DD R5DD R6DD R0PU R2PU R3PU R0CR R2CR R3CR IEDS PMR IENL IENH IRQL IRQH SMR WDTR TM0 T0 TDR0 CDR0 TM1 TDR1 T1 CDR1 TM2 Table 8-1 Control Registers R/W R/W R/W R/W R/W R/W R/W W W W W W W W W W W W W R/W R/W R/W R/W R/W R/W W R/W R/W R W R R/W W R R R/W Initial Value
76543210
Page page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 32 page 60 page 60 page 59 page 59 page 76 page 74 page 43 page 43 page 43 page 43 page 43 page 43 page 43 page 43 page 44
00000000 - - - -000-------0 00000000 - - - -0000 - - - 00000 00000000 - - - -000-------0 00000000 - - - -0000 - - - 00000 00000000 - - - -000-------0 00000000 - - - -000-------0 - - 000000 0 - - 00000 - - 000000 0 - - 00000 - - 000000 -------0 - - - 10010 - - 000000 00000000 11111111 00000000 - - - 00000 11111111 00000000 00000000 - - 000000
- - 0 0 0 0 0 0 page 32, page 57
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Address
Register Name Timer2 Counter Register
Symbol T2 TDR2 CDR2 TM3 TDR3 T3 CDR3 ADCM ADR WTMR LCR LPMR RPR BITR CKCTLR SCMR LVDR BUR SIOM SIOR Table 8-1 Control Registers
R/W R W R R/W W R R R/W R R/W R/W R/W R/W R W R/W R/W W R/W R/W
Initial Value
76543210
Page page 44 page 44 page 44 page 44 page 44 page 44 page 44 page 53 page 53 page 74 page 66 page 66 page 41 page 41 page 37 page 82 page 57 page 54 page 54
00000000 11111111 00000000 - - - 00000 11111111 00000000 00000000 - 0000001 Undefined -0 - -0000 - 0000000 - -000000 00000000 - - - 00111 00000000 00000 - - 00000000 00000001 Undefined
00E7 00E8 00E9 00EA 00EC 00ED 00EF 00F1 00F2 00F3 00F4 00F5 00FB 00FD 00FE 00FF
Timer2 Data Register Timer2 Input Capture Register Timer3 Mode Register Timer3 Data Register Timer3 Counter Register Timer3 Input Capture Register A/D Converter Mode Register A/D Converter Data Register Watch Timer Mode Register LCD Control Register LCD Port Mode Register High RAM Paging Register Basic Interval Timer Register Clock Control Register System Clock Mode Register LVD Register Buzzer Data Register Serial I/O Mode Register Serial I/O Data Register
- - - - - - 0 0 page 23, page 66
W R/W
Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. Registers are controlled by both bit and byte manipulation instruction.
- : this bit location is reserved.
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GMS81C7208/7216
Three registers are mapped on same address. Address E1H E3H E4H E7H E9H EAH Timer/Counter Mode T0 [R], TDR0 [W] TDR1 [W] T1 [R] T2 [R], TDR2 [W] TDR3 [W] T3 [R] Capture Mode CDR0 [R], TDR0 [W] TDR1 [W] CDR1 [R] CDR2 [R], TDR2 [W] TDR3 [W] CDR3 [R]
Two registers are mapped on same address. Address F4H Basic Interval Timer BITR [R], CKCTLR [W]
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8.5 Addressing Mode
The G(H)MS800 series MCU uses six addressing modes; E45535 LDM 35H,#55H
* Register Addressing * Immediate Addressing * Direct Page Addressing * Absolute Addressing * Indexed Addressing * Register Indirect Addressing
0F100H 0F101H 0F102H 0135H data data 55H
~ ~
E4 55 35
~ ~
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing #imm
In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC #35H
MEMORY
(3) Direct Page Addressing dp
In this mode, a address is specified within direct page. Example; G=0 C535 LDA 35H ;A RAM[35H]
35H 04 35
data
~ ~
A+35H+C A
~ ~
0E550H 0E551H C5 35
data A
When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=01
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(4) Absolute Addressing !abs
Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ROM[0F035H]
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1 D4 LDA {X} ;ACCRAM[X]
115H
data
~ ~
data A
~ ~
0E550H D4
0F035H
data
~ ~
~ ~
0F100H 0F101H 0F102H 07 35 F0
A+data+C A
X Indexed Direct Page, Auto Increment {X}+
In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H
address: 0F035
The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag. 983501 INC !0135H ;A ROM[135H]
DB
LDA
{X}+
35H
data
~ ~
data A
~ ~
DB 135H data
36H X
~ ~
~ ~
0F100H 0F101H 0F102H 98 35 01

data+1 data
address: 0135
X Indexed Direct Page (8 Bit Offset) dp+X
This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H
(5) Indexed Addressing X Indexed Direct Page (No Offset) {X}
In this mode, a address is specified by the X register.
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C645
LDA
45H+X
Example; G=0 3F35 JMP [35H]
3AH
data
35H
0A E3
~ ~
0E550H 0E551H C6 45
36H
~ ~

data A 0E30AH
~ ~
NEXT
~ ~
jump to address 0E30AH
45H+0F5H=13AH
~ ~
0FA00H 3F 35
~ ~
Y Indexed Direct Page (8 Bit Offset) dp+Y
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X.
X Indexed Indirect [dp+X]
Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H 1625 ADC [25H+X]
Y Indexed Absolute !abs+Y
Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole area. Example; Y=55H D500FA LDA !0FA00H+Y
35H 36H 0F100H 0F101H 0F102H D5 00 FA
05 E0
0FA00H+55H=0FA55H
~ ~
0E005H data
~ 0E005H ~
~ ~
25 + X(10) = 35H
~ ~
0FA00H 16 25
~ ~
0FA55H data
~ ~

data A
A + data + C A Y Indexed Indirect [dp]+Y
Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Yregister data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H
(6) Indirect Addressing Direct Page Indirect [dp]
Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL
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1725
ADC
[25H]+Y
Example; G=0 1F25E0 JMP [!0E025H]
25H 26H
05 E0 PROGRAM MEMORY
~ ~
0E015H data
~ ~
0E005H + Y(10) = 0E015H
0E025H 0E026H
25 E7
~ ~
0FA00H 17 25
~ ~
~ ~
~ ~
NEXT
A + data + C A
0E725H
jump to address 0E30AH
~ ~
0FA00H 1F 25 E0
~ ~
Absolute Indirect [!abs]
The program jumps to address specified by 16-bit absolute address. JMP
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9. I/O PORTS
The GMS81C7208/16 has six ports (R0, R2, R3, R4, R5 and R6), and LCD segment port SEG0~SEG11 and SEG16~SEG20 and LCD common port COM0~COM3, which are multiplexed with SEG24~SEG26. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, in a initial reset state, R0,R2,R3 ports are used as a general purpose input port and R4, R5 and R6 ports are used as LCD segment drive output port.
9.1 Port Data Registers
Port Data Registers
The Port Data Registers in I/O buffer in each six ports (R0,R2,R3,R4,R5,R6) are represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to "read data register" signal from the CPU. Some instructions that read a port activating the "read register" signal, and others activating the "read pin" signal When a port is used as input, input logic is firmly either low or high, therefore external pull-down or pull-up resisters are required practically. The GMS81C7208/16 has internal pull-up, it can be logic high by pull-up that can be able to configure either connect or disconnect individually by pull-up control registers R0PU, R2PU and R3PU. When ports are configured as inputs and pull-up resistor is selected by software, they are pulled to high.
Port Direction Registers
All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C8H (R0 port direction register) during initial setting as shown in Figure 9-1.
VDD
VDD
PULL-UP RESISTOR Typ. 160k
PORT PIN
GND
Pull-up control bit 0: Disconnect 1: Connect
WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H 0C1H R0 DATA R1 DATA 01010101 76543210 BIT
Figure 9-2 Pull-up Port Structure
Open Drain Port Registers
The R0, R2 and R3 ports have open drain port resistors R0CR~R3CR. Figure 9-3 shows a open drain port configuration by control register. It is selected as either push-pull port or open-drain port by R0CR, R1CR, R2CR and R3CR.
~ ~
0C8H 0C9H R0 DIRECTION R1 DIRECTION
~ ~
IOIOIO I O PORT 76543210 I : INPUT PORT O : OUTPUT PORT
Figure 9-1 Example of Port I/O Assignment
PORT PIN
All the port direction registers in the MCU have 0 written to them by reset function. On the other hand, its initial status is input.
GND
Open drain port selection bit 0: Push-pull 1: Open drain
Pull-up Control Registers
The R0, R2 and R3 ports have internal pull-up resistors. Figure 9-2 shows a functional diagram of a typical pull-up port. It is connected or disconnected by pull-up control register (PURn). The value of that resistor is typically 160k. Figure 9-3 Open Drain Port Structure
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9.2 I/O Ports Configuration
R0 and R0DD Register: R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C8H). Each port also can be set individually as pull-up port through the R0PU (address 0D0H), and as open drain register through the R0CR (address 0D4H). In addition, port R0 is multiplexed with various special features. The control register through the PMR (address 0D9H) and the SIOM (address 0FEH) control the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input, serial interface data input, serial interface data output or serial interface clock, write "1" in the corresponding bit of PMR (address 0D9H) and SIOM (address 0FEH). Port Pin R00 R01 R02 R03 R04 R05 R06 R07 Alternate Function INT0 (External interrupt 0) INT1 (External interrupt 1) INT2 (External interrupt 2) EC0 (Event counter input 0) EC2 (Event counter input 2) SCK (Serial clock) SO (Serial data output) SI (Serial data input) . R0 Pull-up Register R0PU
Port Pull-up 0: Pull-up Resistor Off 1: Pull-up Resistor On ADDRESS: 0D0H RESET VALUE: 00H
R0 Open Drain Control Register ADDRESS: 0D4H R0CR
Port Open drain 0: Push Pull 1: Open Drain
RESET VALUE: 00H
Port Mode Register PMR
5 4 3
ADDRESS: 0D9H RESET VALUE: 00H 2 1 0 0: R00 1: INT0 0: R01 1: INT1 0: R02 1: INT2 0: R03 1: EC0
0: R04 1: EC2 0: R30 1: BUZ
Regardless of the direction register R0DD, the control registers of PMR and SIOM are selected to use as alternate functions, port pin can be used as a corresponding alternate features. . R0 Data Register R0
ADDRESS: 0C0H RESET VALUE: 00H
R07 R06 R05 R04 R03 R02 R01 R00 Input / Output data
Edge Detection Register IEDS
5 4 3 2
ADDRESS: 0D8H RESET VALUE: 00H 1 0 INT0
INT2
INT1
R0 Direction Register R0DD
ADDRESS: 0C8H RESET VALUE: 00H
External Interrupt Edge Select 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)
Port Direction 0: Input 1: Output
R2 and R2DD Register: R2 is an 3-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R2DD register (address 0CAH). Each port also can be set individually as pull-up port through the R2PU (address 0D2H), and as open drain register through the R2CR (address 0D6H).
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In addition, port R2 is multiplexed with analog input port. Port Pin R21 R22 R23 Alternate Function AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3)
R3 and R3DD Register: R3 is an 1-bit CMOS bidirectional I/O port (address 0C3H). Each I/O pin can independently used as an input or an output through the R3DD register (address 0CBH). Each port also can be set individually as pull-up port through the R3PU (address 0D3H), and as open drain register through the R3CR (address 0D7H). In addition, port R3 is multiplexed with various special features. Port Pin Alternate Function BUZ (Buzzer driving output)
R2 Data Register R2
-
ADDRESS: 0C2H RESET VALUE: 00H R23 R22 R21 -
R30
Input / Output Data
R3 Data Register R3
-
ADDRESS: 0C3H RESET VALUE: 00H R30
R2 Direction Register R2DD
-
ADDRESS: 0CAH RESET VALUE: 00H -
Input / Output data
Port Direction 0: Input 1: Output
R3 Direction Register R3DD
-
ADDRESS: 0CBH RESET VALUE: 00H -
R2 Pull-up Register R2PU
-
ADDRESS: 0D2H RESET VALUE: 00H Port Pull-up 0: Pull-up Resistor Off 1: Pull-up Resistor On
Port Direction 0: Input 1: Output
R3 Pull-up Register R3PU
-
ADDRESS: 0D3H RESET VALUE: 00H -
R2 Open Drain Control Register ADDRESS: 0D6H R2CR
-
RESET VALUE: 00H
Port Pull-up 0: Pull-up Resistor Off 1: Pull-up Resistor On
Port Open Drain 0: Push Pull 1: Open Drain
R3 Open Drain Control Register ADDRESS: 0D7H R3CR
-
RESET VALUE: 00H
Port Open Drain 0: Push Pull 1: Open drain
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Port Selection Register PMR
5 4 3
ADDRESS: 0D9H RESET VALUE: 00H 2 1 0 0: R00 1: INT0 0: R01 1: INT1 0: R02 1: INT2 0: R03 1: EC0
R4 and R4DD Register: R4 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0CCH). After Reset, R4 port is used as LCD segment output SEG0~SEG7. To use general I/O ports user should be written appropriate value into the LPMR (0F3H). LCD Pin Function SEG0 (LCD Segment 0 Signal Output) SEG1 (LCD Segment 1 Signal Output) SEG2 (LCD Segment 2 Signal Output) SEG3 (LCD Segment 3 Signal Output) SEG4 (LCD Segment 4 Signal Output) SEG5 (LCD Segment 5 Signal Output) SEG6 (LCD Segment 6 Signal Output) SEG7 (LCD Segment 7 Signal Output) Port Pin R40 R41 R42 R43 R44 R45 R46 R47
0: R04 1: EC2 0: R30 1: BUZ
Watch Dog Timer Register WDTR
WDEN
ADDRESS: 0DFH RESET VALUE: --01_0010B
WDOM WDCLR
WDCK1 WDCK0
R4 Data Register LCD Control Register LCR
ADDRESS: 0F1H RESET VALUE: 00H
ADDRESS: 0C4H RESET VALUE: 00H
R4
R47 R46 R45 R44 R43 R42 R41 R40 Input / Output data
SUBM BTC LCDEN BRC DTY1 DTY0 LCK1 LCK0
** Caution : The bit7(SUBM) of LCR register must be set to "1" by software because of reduction current consumption (reset value="0").
R4 Direction Register R4DD
ADDRESS: 0CCH RESET VALUE: 00H
Port Direction 0: Input 1: Output
R5 and R5DD Register: R5 is an 4-bit CMOS bidirectional I/O port (address 0C5H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0CDH). After Reset, R5 port is used as LCD segment output SEG8~SEG11. To use general I/O ports user should be written appropriate value into the LPMR (0F3H). LCD Pin Function SEG8 (LCD Segment 8 Signal Output) SEG9 (LCD Segment 9 Signal Output) SEG10 (LCD Segment 10 Signal Output) SEG11 (LCD Segment 11 Signal Output) Port Pin R50 R51 R52 R53
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appropriate value into the LPMR (0F3H). R5 Data Register R5
ADDRESS: 0C5H RESET VALUE: 00H R53 R52 R51 R50
LCD Pin Function SEG16 (LCD Segment 16 Signal Output) SEG17 (LCD Segment 17 Signal Output) SEG18 (LCD Segment 18 Signal Output) SEG19 (LCD Segment 19 Signal Output) SEG20 (LCD Segment 20 Signal Output)
Port Pin R60 R61 R62 R63 R64
Input / Output Data
R5 Direction Register R5DD
-
ADDRESS: 0CDH RESET VALUE: 00H
Port Direction 0: Input 1: Output
R6 Data Register R6
-
ADDRESS: 0C6H RESET VALUE: 00H R64 R63 R62 R61 R60
R6 and R6DD Register: R6 is an 5-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin can independently used as an input or an output through the R6DD register (address 0CEH). After Reset, R6 port is used as LCD segment output SEG16~SEG20. To use general I/O ports user should be written R6DD
-
Input / Output Data
R6 Direction Register
Port Direction 0: Input 1: Output
ADDRESS: 0CEH RESET VALUE: 00H
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10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains an oscillators: a main-frequency clock oscillator. The system clock can also be obtained from the external oscillator. The clock generator produces the system clocks forming clock pulse, which are supplied to the CPU and the peripheral hardware. The internal system clock can be selected by bit2, and bit3 of the system clock mode register(SCMR). CPU Clock /2 /8 / 16 / 64 The register is shown in Figure 10-2. To the peripheral block, the clock among the not-divided original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by STOP instruction. Instruction Cycle Time XIN = 4MHz 0.5 us 2.0 us 4.0 us 16.0 us
SYCC<1>=0 & LCR<7>=1 SYCC<0>
STOP Mode
SLEEP Mode
SCS[1:0] Select clock CLOCK PULSE GENERATOR
OSC Stop
/2 /8 /16 /64 MUX
XIN PIN Reserved
0 1
fEX
Internal system clock (CPU clock)
SYCC<1>=1 & LCR<7>=0 PRESCALER PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512 /1024
Peripheral clock
fEX(MHz)
4 Frequency period
PS0 4M 250n
PS1 2M 500n
PS2 1M 1u
PS3 500K 2u
PS4 250K 4u
PS5 125K 8u
PS6 62.5K 16u
PS7 31.25K 32u
PS8 15.63K 64u
PS9
PS10
7.183K 3.906K 128u 256u
Figure 10-1 Block Diagram of Clock Generator
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The system clock is decided by bit1 (SYCC1) of the system clock mode register(SCMR). On the initial reset, internal system clock
is PS1 which is the fastest and other clock can be provided by bit2 and bit3 of SCMR.
SCMR
7 -
6 -
5 -
4 -
R/W R/W R/W R/W 3 2 1 0 BTCL SCS0 SYCC1 SYCC0 SCS1
ADDRESS: 0F5H INITIAL VALUE: 00H System (CPU) Clock Control 00: Main Clock On 01: Main Clock On 10: Reserved 11: Reserved System Clock Source Select 00: XIN/2 01: XIN/8 10: XIN/16 11: XIN/64
Figure 10-2 SCMR: System Clock Control Registers
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11. OPERATION MODE
The system clock controller starts or stops the main-frequency clock oscillator. The operating mode is generally divided into the main-clock mode, which is controlled by system clock mode register (SCMR). Figure 11-1shows the operating mode transition diagram. System clock control is performed by the system clock mode register, SCMR. During reset, this register is initialized to "0" so that the main-clock operating mode is selected. The CPU and the peripheral hardwares are operated on the highfrequency clock. At reset release, this mode is invoked.
SLEEP Mode
In this mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally.
STOP Mode
In this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level.
Main Clock Operating Mode
This mode is fast-frequency operating mode.
Main - Oscillating
Main-clock Mode
tr u
Release
NOTE1:
OP I
r to
RESET Watch Timer Int. Timer interrupt (EC0, EC2) External Int. SIO Int. Watchdog Timer Int. RESET All Int.
Reset
cti o
n
tr u In s
te 1
Re
ns
no
fe r to
o cti
ST
n
no
Re fe
te 2
RESET Operation
NOTE2:
t se Re
Main: Oscillating
Re s
et
Main: Stopped
STOP Mode
SLEEP Mode
Main: According to SCMR
CPU and Peripherals are stops,
CPU stops, Peripherals are operate.
Figure 11-1 Operating Mode
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11.1 Operation Mode
In the main-clock operation mode, only the high-frequency clock oscillator is used. During reset, the system clock mode register is initialized at the main-clock mode. eration is released by reset, the operation mode is to main-clock mode. The methods of release are RESET, watch timer interrupt, Timer/ Event Counter1 (EC0, EC2 pin), and external interrupt. For more details, see "20.2 STOP Mode" on page 77. Note: In the STOP, the power consumed by the oscillator and the internal hardware is reduced. However, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. This must be considered in system design as well as interface circuit design.
Shifting from the Normal Operation to the SLEEP Mode
By setting bit 0 of SMR, the CPU clock stops and the SLEEP mode is invoked. The CPU stops while other peripherals are operate normally. The way of release from this mode is RESET and all available interrupts. For more detail, See "20.1 SLEEP Mode" on page 76
Shifting from the Normal Operation to the STOP Mode
By executing STOP instruction, the main-frequency clock oscillation stops and the STOP mode is invoked. After the STOP op-
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12. BASIC INTERVAL TIMER
The GMS81C7208/16 has one 8-bit basic interval timer that is free-run and can not stop. Block diagram is shown in Figure 12-1. In addition, the basic tnterval timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The basic interval timer is controlled by the clock control register (CKCTLR) shown in Figure 12-2. Source clock can be selected by lower 3 bits of CKCTLR. The registers BITR and CKCTLR are located at same address, and address 0F9H is read as a BITR, and written to CKCTLR.
SCMR[1:0]
0X 1X
/8 /16 /32
Prescaler
fXIN reserved
/64 /128 /256 /512 /1024
MUX
source clock [0F9H]
8-bit up-counter
overflow
BITIF Basic Interval Timer Interrupt To Watchdog timer (WDTCK)
clear
Select Input clock 3 BTS[2:0] [0F4H] Basic Interval Timer clock control register Internal bus line CKCTLR BTCL BITR Read
Figure 12-1 Block Diagram of Basic Interval Timer
BTS[2:0] 000 001 010 011 100 101 110 111
CPU Source Clock /8 /16 /32 /64 /128 /256 /512 /1024
Interrupt (overflow) Period (ms) @ fXIN = 4MHz 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536
Table 12-1 Basic Interval Timer Interrupt Time
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CKCTLR
7 -
6 -
5 -
W W W W 3 2 1 0 BCK BTCL BTS2 BTS1 BTS0 BTCL
W 4
ADDRESS: 0F4H INITIAL VALUE: ---0 0111B
Caution:
Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.
Basic Interval Timer source clock select 000: fXIN / 8 001: fXIN / 16 010: fXIN / 32 011: fXIN / 64 100: fXIN / 128 101: fXIN / 256 110: fXIN / 512 111: fXIN / 1024 Clear bit 0: Normal operation, free-run 1: Clear 8-bit counter (BITR) to "0" and count up again. This bit becomes to "0" automatically after one machine cycle. For the test purpose. This bit must be cleared to "0" for normal operation, otherwise BIT clock source is form sub-clock.
R 7
R 6
R 5
R 4
BITR
R 3 BTCL
R 2
R 1
R 0
ADDRESS: 0F4H INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
Figure 12-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. : LDM SET1 EI : CKCTLR,#0CH BITE
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13. TIMER/EVENT COUNTER
The GMS81C7208/16 has four Timer/Event Counters. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and timer 1 are can be used either two 8-bit Timer/ Counter or one 16-bit Timer/Counter with combine them. Also timer 2 and timer 3 can be joined as a 16-bit Timer/Counter. In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. The count rate is 1/2 to 1/2048 of the oscillator frequency. In the "counter" function, the register is incremented in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0 or EC2 pin. In addition the "capture" function, the register is incremented in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into capture data register correspondingly. It has five operating modes: "8-bit Timer/Counter", "16-bit Timer/Counter", "8-bit capture", "16-bit capture" which are selected by bit in timer mode register TMn. In operation of timer 2, timer 3, their operations are same with timer 0, timer 1, respectively. When programming the software, you may refer to following example.
Example 1: Timer 0 = 8-bit timer mode, 8ms interval at 4MHz Timer 1 = 8-bit timer mode, 4ms interval at 4MHz Timer 2 = 16-bit event counter mode LDM LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 EI : : Example 2: Timer0 = 16-bit timer mode, 0.5s at 4MHz Timer2 = 2ms 8-bit timer mode at 4MHz Timer3 = 250us 8-bit timer mode at 4MHz LDM LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 EI : : SCMR,#0 ;Main clock mode TDR0,#23H TDR1,#0F4H TM0,#0FH ;FXIN/32, 8us TM1,#4CH TDR2,#249 TDR3,#124 TM2,#0FH TM3,#0DH T0E T2E T3E SCMR,#0 ;Main clock mode TDR0,#249 TM0,#0001_0011B TDR1,#124 TM1,#0000_1111B TDR2,#1FH TDR3,#4CH TM2,#0001_1111B TM3,#0100_1100B T0E T2E
Example 3: Timer0 = 8-bit timer mode, 2ms interval at 4MHz Timer1 = 8-bit capture mode, 2us sampling count. LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 EI : : X: don't care. Example 4: Timer0 = 8-bit timer mode, 2ms interval at 4MHz Timer2 = 16-bit capture mode, 8us sampling count. LDM LDM LDM LDM LDM LDM LDM LDM TDR0,#249 TM0,#0FH IEDS,#XX11_XXXXB PMR4,#XXXX_X1XXB TDR2,#0FFH TDR3,#0FFH TM2,#XX10_1111B TM3,#X10X_11XXB TDR0,#249 TM0,#0FH ;250x8=2000us ;FXIN/32, 8us ;FALLING ;AS INT1 ;2us
IEDS,#XXXX_01XXB PMR,#XXXX_XX1XB TDR1,#0FFH TM1,#0001_1011B T0E T1E INT1E
;ENABLE TIMER 0 ;ENABLE TIMER 1 ;ENABLE EXT. INT1
;MAX ;MAX ;/32
;FXUN/32, 8us ;FXIN/8, 2us
SET1 SET1 SET1 EI : : X: don't care.
T0E T2E INT2E
;ENABLE TIMER 0 ;ENABLE TIMER 2 ;ENABLE EXT. INT2
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Timer 0 Mode Register
7 6 -
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T0ST
TM0
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN BTCL
ADDRESS: 0E0H INITIAL VALUE: 00H
Timer/Counter 0 Start/Stop Control Flag 0: Stop Count 1: Clearing the T0 Counter and Start Again Timer/Counter 0 Enable Flag 0: Disable Count 1: Enable Count Basic Interval Timer Source Clock Selection 000: fXIN / 2 001: fXIN / 4 010: fXIN / 8 011: fXIN / 32 100: fXIN / 128 101: fXIN / 512 110: fXIN / 2048 111: EC0 (External Event Input 0) Capture Mode Enable 0: Timer Mode 1: Capture Mode
Timer 1 Mode Register TM1
R/W 7 -
R/W 6 16BIT0
R/W 5 -
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T1ST
BTCL CAP1 T1CK1 T1CK0 T1CN
ADDRESS: 0E2H INITIAL VALUE: 00H
Timer/Counter 1 Start/Stop Control Flag 0: Stop Count 1: Clearing the T1 Counter and Start Again Mode Selection 0: 8-bit Mode 1: 16-bit Mode Timer/Counter 1 Enable Flag 0: Disable Count 1: Enable Count Timer/Counter 1 Source Clock Selection 00: fXIN 01: fXIN / 2 10: fXIN / 8 11: Timer 0 Clock Capture Mode Enable 0: Timer Mode 1: Capture Mode
TDR0~TDR3
W 7
W 6
W 5
W 4
W 3
W 2
W 1
W 0
ADDRESS: 0E1H, 0E3H, 0E7H, 0E9H INITIAL VALUE: 0FFH
Compare data registers
Figure 13-1 TM0, TM1, TDRn Registers
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Timer 2 Mode Register
7 6 -
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T2ST
TM2
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN BTCL
ADDRESS: 0E6H INITIAL VALUE: 00H
Timer/Counter 2 Start/Stop Control Flag 0: Stop Count 1: Clearing the T0 Counter and Start again Timer/Counter 2 Enable Flag 0: Disable Count 1: Enable Count Timer/Counter 2 Source Clock Select 000: fXIN / 2 001: fXIN / 4 010: fXIN / 8 011: fXIN / 32 100: fXIN / 128 101: fXIN / 512 110: fXIN / 2048 111: EC2 (External Event Input 2) Capture Mode Enable 0: Timer Mode 1: Capture Mode
Timer 3 Mode Register TM3
R/W 7 -
R/W 6 16BIT1
R/W 5 -
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 T3ST
BTCL CAP3 T3CK1 T3CK0 T3CN
ADDRESS: 0E8H INITIAL VALUE: 00H
Timer/Counter 3 Start/Stop Control Flag 0: Stop Count 1: Clearing the T3 Counter and Start Again Mode Selection 0: 8-bit Mode 1: 16-bit Mode Timer/Counter 3 Enable Flag 0: Disable Count 1: Enable Count Timer/Counter 3 Source Clock Selection 00: fXIN 01: fXIN / 2 10: fXIN / 8 11: Timer 2 Clock Capture Mode Enable 0: Timer Mode 1: Capture Mode
T0~T3 CDR0~CDR3
R 7
R 6
R 5
R 4
R 3
R 2
R 1
R 0
ADDRESS: 0E1H, 0E4H, 0E7H, 0EAH INITIAL VALUE: 00H
Count registers
Figure 13-2 TM2, TM3 Registers
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13.1 8-bit Timer / Counter Mode
The GMS81C7208/16 has four 8-bit Timer/Counters, timer 0, timer 1, timer 2, timer 3 which are shown in Figure 13-3, Figure 13-4. The "timer" or "counter" function is selected by control registers TMn. To use as an 8-bit Timer/Counter mode, CAP0, CAP1 and
7 6 X
16BIT0 bits should be cleared to "0". These timers have each 8bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2~2048 selected by control bits of register TMn (n=0,1,2,3).
5
0
4
X
3
X
2
X
1
X
0
X
TM0
X
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL
ADDRESS: 0E0H INITIAL VALUE: 00H
TM1
X
16BIT0 0
0
CAP1 T1CK1 T1CK0 T1CN T1ST BTCL
0 X X X X
ADDRESS: 0E2H INITIAL VALUE: 00H
T0CK[2:0] Edge Detector
X means don't care
EC0 PIN
SCMR[1:0] Prescaler fXIN reserved
0X 1X
111
/ 2048 / 512 / 128 / / / / 32 8 4 2
110 101 100 011 010 001 000
0 1 T0CN [0E1H]
T0ST 0: Stop 1: Clear and start T0 (8-bit) clear T0IF Comparator TDR0 (8-bit) [0E1H] TIMER 0 INTERRUPT
MUX
TIMER 0
T1CK[1:0] T1ST /8 /2 /1
11 10 01 00
0: Stop 1: Clear and start 0 1 T1CN Comparator TDR1 (8-bit) [0E3H] T1 (8-bit) [0E4H] T1IF TIMER 1 INTERRUPT clear
MUX
TIMER 1
Figure 13-3 8-bit Timer/Counter 0, 1
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Note: The contents of timer data register TDRx should be initialized with 1H~FFH, not to 0H, because it is not to defined before reset. In the timer 0, timer register T0 increments from 00H until it matches with TDR0 and then reset to 00H. The match output of timer 0 generates timer 0 interrupt (latched in T0IF bit)
7 6 X
As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. In counter function, the counter is increased every 0-to-1 (rising edge) transition of EC0 or EC2 pin. In order to use counter function, the bit 3 and bit 4 of the Port mode register PMR are set to "1" by software. The Timer 0 can be used as a counter by pin EC0 input. Similarly, Timer 2 can be used by pin EC2 input.
5
0
4
X
3
X
2
X
1
X
0
X
TM2
X
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL
ADDRESS: 0E6H INITIAL VALUE: 00H
TM3
X
16BIT1 0
0
CAP3 T3CK1 T3CK0 T3CN T3ST BTCL
0 X X X X
ADDRESS: 0E8H INITIAL VALUE: 00H
T2CK[2:0] Edge Detector
X means don't care
EC2 PIN
SCMR[1:0] Prescaler fXIN reserved
0X 1X
111
/ 2048 / 512 / 128 / / / / 32 8 4 2
110 101 100 011 010 001 000
0 1 T2CN
T2ST 0: Stop 1: Clear and start T2 (8-bit) [0E7H] T2IF Comparator TDR2 (8-bit) [0E7H] clear TIMER 2 INTERRUPT
MUX
TIMER 2
T3CK[1:0] T3ST /8 /2 /1
11 10 01 00
0: Stop 1: Clear and start 0 1 T3CN Comparator TDR3 (8-bit) [0E9H] T3 (8-bit) [0EAH] T3IF TIMER 3 INTERRUPT clear
MUX
TIMER 3
Figure 13-4 8-bit Timer/Counter 2, 3
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8-bit Timer Mode
In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn (n=0,1,2,3) are compared with the contents of up-counter, Tn (n=0,1,2,3). If match is found, a timer 1 interrupt
Start count
(T1IF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn can be re-written by software, time interval is set as you want.
Source clock Up-counter TDR1 T1IF interrupt
0 n 1 2 3
Figure 13-5 Timer Mode Timing Chart
Example: Make 1ms interrupt using by Timer0 at 4MHz LDM LDM SET1 EI
When
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Match Detect n-2 n-1 n 0 1 2 3 4 Counter Clear
TM0,#0FH TDR0,#124 T0E
; ; ; ;
divide by 32 8us x (124+1)= 1ms Enable Timer 0 Interrupt Enable Master Interrupt
TM0 = 0000_1111B (8-bit Timer mode, Prescaler divide ratio /32) TDR0 = 124D = 7CH fXIN = 4 MHz 1 INTERRUPT PERIOD = x 32 x (124+1) = 1 ms 4 x 106 Hz TDR1 7D MATCH (TDR0 = T0) 7B 7A
~~
7D 7C 8 s
Count Pulse Period
~~
up
-c o ~~
un
t
6 5 4 3 2 1
0
0 Interrupt period = 8 s x 125
TIME
Timer 1 (T1IF) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 13-6 Timer Count Example
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8-bit Event Counter Mode
In this mode, counting up is started by an external trigger. This trigger means rising edge of the EC0 or EC2 pin input. Source clock is used as an internal clock selected with timer mode register TM0, TM1, TM2 or TM3. The contents of timer data register TDRn (n = 0,1,2,3,........,FF) are compared with the contents of the up-counter Tn. If a match is found, an timer interrupt request flag TnIF is generated, and the counter is cleared to "0". The counter is restart and count up continuously by every rising edge of the ECn pin input. The maximum frequency applied to the ECn pin is fXIN/2 [Hz]. In order to use event counter function, the bit 3, 4 of the Port Mode Register PMR (address 0D9H) is required to be set to "1".
Start count ECn pin input ~ ~ ~ ~
After reset, the value of timer data register TDRn is undefined, it should be initialized to between 01H~FFH, not to "0". The interval period of Timer is calculated as below equation.
1Period (sec) = --------- x 2 x Divide Ratio x TDRn f XIN
Up-counter TDR1 T1IF interrupt
0 n
1
2
n-1
n
0
1
2
Figure 13-7 Event Counter Mode Timing Chart
~ ~ ~ ~ ~ ~ ~ ~
TDR1 disable enable
clear & start stop
up
-c o
un
t
~ ~
~ ~
TIME Timer 1 (T1IF) Interrupt Occur interrupt T1ST = 1 T1ST = 0 T1CN = 1 T1CN = 0 Occur interrupt
T1ST Start & Stop T1CN Control count
Figure 13-8 Count Operation of Timer / Event Counter
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13.2 16-bit Timer / Counter Mode
The Timer register is being run with all 16 bits. A 16-bit Timer/ Counter register T0, T1 are incremented from 0000H until it matches TDR0, TDR1 and then resets to 0000H. The match output generates Timer 0 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0SL1, T0SL0.
7 TM0 X
Even if the Timer 0 (including the Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8bit timer or one 16-bit timer by setting the TM2. Reversely, even if the Timer 2 (including the Timer 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer independently.
2
X
6 X 16BIT0 1
5
0 0
4
X
3
X
1
X
0
X
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST BTCL
ADDRESS: 0E0H INITIAL VALUE: 00H ADDRESS: 0E2H INITIAL VALUE: 00H
TM1
X
BTCL CAP1 T1CK1 T1CK0 T1CN T1ST
0 1 1 X X
X means don't care T0CK[2:0] Edge Detector T0ST 0: Stop 1: Clear and start T1 (16-bit) T0CN Comparator TDR1 Higher byte TDR0 Lower byte T0 clear T0IF TIMER 0 INTERRUPT (Not Timer 1 interrupt)
EC0 PIN
SCMR[1:0]
0X 1X
111
Prescaler
fXIN reserved
/ 2048 / 512 / 128 / / / / 32 8 4 2
0
110 101 100 011 010 001 000
1
MUX TIMER 0 + TIMER 1 TIMER 0 (16-bit)
COMPARE DATA
7 TM2 X
6 X 16BIT1 1
5
0 0
4
X
3
X
2
X
1
X
0
X
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST BTCL
ADDRESS: 0E6H INITIAL VALUE: 00H ADDRESS: 0E8H INITIAL VALUE: 00H
TM3
X
CAP3 T3CK1 T3CK0 T3CN T3ST BTCL
0 1 1 X X
X means don't care T2CK[2:0] Edge Detector
EC2 PIN
SCMR[1:0]
1X 1X
111
Prescaler
fXIN reserved
/ 2048 / 512 / 128 / / / / 32 8 4 2
0
110 101 100 011 010 001 000
T2ST 0: Stop 1: Clear and start T3 (16-bit) T2 clear T2IF Comparator TDR3 Higher byte TDR2 Lower byte TIMER 2 INTERRUPT (Not Timer 3 interrupt)
1 T2CN
MUX TIMER 0 + TIMER 1 TIMER 0 (16-bit)
COMPARE DATA
Figure 13-9 16-bit Timer/Counter
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13.3 8-bit Capture Mode
The capture mode can be used to measure the pulse width between two edges. The timer 0 capture mode is set by bit CAP0 of timer mode register TM0, and the timer 1 capture mode is set by CAP1 of timer mode register TM1 as shown in Figure 13-10. Timer 2 and timer 3 have same architecture with timer 0 and timer 1. The Timer/Counter register is incremented in response internal or external input. This counting function is same with normal timer mode, and timer interrupt is generate when timer register T0 (T1, T2, T3) increase and match TDR0 (TDR1, TDR2, TDR3).
7 TM0 X
Timer/Counter still does the above, but with the added feature that a edge transition at external input INTn pin causes the current . f xin f timer = ------------------------------------------------------------------------------2 x prescaler value x ( TDR + 1 )
6 X 16BIT0 0
5
1 0
4
X
3
X
2
X
1
X
0
X
BTCL CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
ADDRESS: 0E0H INITIAL VALUE: 00H ADDRESS: 0E2H INITIAL VALUE: 00H
TM1
X
BTCL CAP1 T1CK1 T1CK0 T1CN T1ST
1 X X X X
IEDS[1:0]
01
INT0 PIN
10 11
INT0IF
INT0 INTERRUPT
T0CK[2:0] Edge Detector
CDR0 CDR0 (8-bit) capture T0ST 0: Stop 1: Clear and start clear TIMER 0 INTERRUPT
EC0 PIN
SCMR[1:0] fXIN reserved
0X 1X / 2048 / 512 / 128 / 32 /8 /4 /2 /1
111 110 101 100 011 010 001 000
clear T0 (8-bit) CDR0 (8-bit) T0CN TDR0 (8-bit) CDR0 (8-bit) COMPARE DATA
Prescaler
fEX
Comparator
T0IF
MUX
01
INT1 PIN
10 11
INT1IF
INT1 INTERRUPT
IEDS[3:2]
CDR1 CDR0 (8-bit) T1CK[1:0]
11 10 01 00
capture clear T1 (8-bit) CDR0 (8-bit) T1CN TDR1 (8-bit) CDR0 (8-bit) COMPARE DATA
T1ST 0: Stop 1: Clear and start clear TIMER 1 INTERRUPT
/8 /2 /1
MUX
Comparator
T1IF
Figure 13-10 8-bit Capture Mode (Timer0/Timer1 Case)
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value in the timer counter register (T0,T1), to be captured and stored into registers CDRn (CDR0, CDR1), respectively. After capture, the Timer counter register is cleared and restarts by hardware. At this time, reading the address E1H as a CDR0, not T0. T0, TDR0, CDR0 are located at same address. The other CDR1~CDR3 are same. Refer to timer registers of page 26. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS. Refer to "17.4 External Interrupt" on page 63. In addition, the transition at INTn pin generate an interrupt.
7 6 X 16BIT0 1
Note: The CDRn and Tn are in same address.In the capture mode, reading operation is read as CDRn, not Tn because addressing path is opened to the CDRn.
5
1 0
4
X
3
X
2
X
1
X
0
X
TM0
X
BTCL CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
ADDRESS: 0E0H INITIAL VALUE: 00H ADDRESS: 0E2H INITIAL VALUE: 00H
TM1
X
CAP1 T1CK1 T1CK0 T1CN T1ST BTCL
1 1 1 X X
X means don't care IEDS[1:0]
01
INT0 PIN
10 11 MSB 16 BITS LSB
INT0IF
INT0 INTERRUPT
T0CK[2:0]
Edge Detector
CDR1
capture
CDR0 T0ST
0: Stop 1: Clear and start
EC0 PIN
SCMR[1:0] fXIN reserved
0X 1X / 2048 / 512 / 128 / 32 /8 /4 /2
111 110 101 100 011 010 001 000
clear clear
T1 T0CN TDR1
T0 T0IF TIMER 0 INTERRUPT
fEX
Prescaler
Comparator
TDR0
MUX
COMPARE DATA
Figure 13-11 16-bit Capture Mode
13.4 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. Configuration is shown in Figure 13-11.
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14. ANALOG DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/ D module has three analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AVDD of ladder resistance of A/D module. The A/D module has two registers which are the control register ADCM and A/D result register ADR. The register ADCM, shown in Figure 14-4, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/ O. To use analog inputs, I/O is selected input mode by R2DD direction register.
How to Use A/D Converter
The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag AIF is set. The block diagram of the A/D module is shown in Figure 14-1. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 20 uS (at fXIN=4 MHz).
"0" AVDD "1" LADDER RESISTOR ADEN
ADS[2:0]
R21/AN1 R22/AN2 R23/AN3
001 010 011
8-bit DAC
S/H Sample & Hold
SUCCESSIVE APPROXIMATION CIRCUIT
ADIF
A/D INTERRUPT
ADR A/D result register
ADDRESS: EDH RESET VALUE: Undefined
Figure 14-1 A/D Block Diagram
A/D Converter Cautions
(1) Input voltage range of AN1 to AN3 The input voltage of AN1 to AN3 should be within the specification range. In particular, if a voltage above AVDD or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. (2) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVDD and AN1 to AN3. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-2 in order to reduce noise.
.
Analog Input 100~1000pF
AN1~AN3
Figure 14-2 Analog Input Pin Connecting Capacitor
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(3) AD pin sharing with normal I/O port The analog input pins AN1 to AN3 also function as input/output port (PORT R21~R23) pins. When A/D conversion is performed with any of pins AN1 to AN3 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AVDD pin input impedance A series resistor string of approximately 10k is connected between the AVDD pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large reference voltage error.
ENABLE A/D CONVERTER A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT A/D START ( ADST = 1 )
NOP NO
ADSF = 1 YES READ ADR
Figure 14-3 A/D Converter Operation Flow
-
R/W 6 ADEN
5 -
R/W 4
R/W
R/W
R/W
R ADDRESS: 0ECH INITIAL VALUE: -0-0 0001B A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit 0: 1: A/D start Setting this bit starts an A/D conversion. After one cycle, bit is cleared to "0" by hardware. Analog input channel select 001: Channel 1 (AN1) 010: Channel 2 (AN2) 011: Channel 3 (AN3)
ADCM
7 -
3 2 1 0 ADS2 BTCL ADS0 ADST ADSF ADS1
A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter R 7 R 6 R 5 R 4 R 3 BTCL R 2 R 1 R 0
ADR
ADDRESS: 0EDH INITIAL VALUE: Undefined
A/D Conversion Data
Figure 14-4 A/D Converter Control Register
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15. SERIAL COMMUNICATION
The serial interface is used to transmit/receive 8-bit data serially. Serial communication block consists of serial I/O data register, serial I/O mode register, clock selection circuit, octal counter and control circuit as illustrated in Figure 15-1.Pin R07/SIN, R06/ SOUT and R05/SCLK pins are controlled by the serial mode register. The contents of the Serial I/O data register can be written into or read out by software. The serial communication is activated by the instruction "SET1 SCK1 0 0 1 1 SCK0 0 1 0 1 SCLK/R05 Port SCLK output SCLK output SCLK output SCLK input SIOST". The octal counter is reset to "0" by this instruction, starts counting at the falling or rising edge (by POL selection) of the transmit clock (SCLK), and it increments at the every clock. A serial interrupt request flag is set when the eighth transmit clock signal is input (the serial interface is reset) or when serial communication is discontinued (the octal counter is reset). The data in the serial data register can be shifted synchronously with the transfer clock signal. Prescaler Divide Ratio /4 / 16 Use clock from Timer 0 overflow -
Clock Source Internal clock Internal clock Internal clock External clock
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R
0
SIOM
POL
MSB
SIO1
SCK1 SIO0 BTCL SCK0 SIOST SIOSF
ADDRESS: 0FEH INITIAL VALUE: 0000_0001B Serial transmission status bit 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to "0" by hardware. Serial transmission clock selection 00: fXIN / 4 01: fXIN / 16 10: Timer 0 Overflow 11: External Clock Serial transmission operation Mode 00: Normal Port(R05,R06,R07) 01: Sending Mode(SCLK,SOUT,R07) 10: Receiving Mode(SCLK,R06,SIN) 11: Sending & Receiving Mode(SCLK,SOUT,SIN) Selection polarity 0: Data in on rising edge, data out on falling edge 1: Data in on falling edge, data out on rising edge
MSB first or LSB first 0: LSB First 1: MSB First
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
SIOR
BTCL
ADDRESS: 0FFH INITIAL VALUE: Undefined
Sending data during sending Mode Receiving data during receiving Mode
Figure 15-1 SCI Control Register
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Serial I/O mode register(SIOM) controls serial I/O function. The POL bit control which edge.
According to SCK1 and SCK0, the internal clock or external clock can be selected. Serial I/O data register(SIOR) is an 8-bit shift register.
SCMR[1:0] Prescaler fXIN reserved T0OV (Timer 0 overflow) R05/SCLK PIN SIO[1:0]
0X 1X /4
SCK[1:0] 00 01
POL
SIOST
start
SIOSF
complete clear
/ 16
CONTROL CIRCUIT
shift clock clock
Edge Detector 10 11 MUX Octal Counter overflow SIOIF Serial communication Interrupt
SCLK OUT
SCK, SIO
R07/SIN PIN SIO1
Serial IO Data [0FFH] SIO0
R06/SOUT PIN
Figure 15-2 Block Diagram of SCI
15.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of SIOM) to "1". After one cycle of SCK, SIOST is cleared automatically to "0". The serial output data from 8-bit shift register is output at falling edge of SCLK. And input data is latched at rising edge of SCLK pin. When transmission clock is counted 8 times, serial I/O counter is cleared as `0". Transmission clock is halted in "H" state and serial I/ O interrupt(SIOIF) occurred.
SIOST SCLK [R05] (POL=0)
SOUT [R06] SIN [R07]
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
SIOSF SIOIF (Interrupt Req.)
Figure 15-3 SPI Timing Diagram at POL=0
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15.2 The Method of Serial I/O
1. Select transmission/receiving mode When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. 2. In case of sending mode, write data to be send to SIOR. 3. Set SIOST to "1" to start serial transmission. If both transmission mode is selected and transmission is performed simultaneously it would be made error. 4. The SIO interrupt is generated at the completion of SIO and SIOSF is set to "1". In SIO interrupt service routine, correct transmission should be tested. 5. In case of receiving mode, the received data is acquired by reading the SIOR.
SIOST SCLK [R05] (POL=1)
SOUT [R06] SIN [R07]
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
SIOSF SCIIF
Figure 15-4 SPI Timing Diagram at POL=1
15.3 The Method to Test Correct Transmission
Serial I/O Interrupt Service Routine 0
SIOSF 1 SE = 0
Abnormal
Write SIOM
- SE : Interrupt Enable Register Low IENL(Bit3) - SR : Interrupt Request Flag Register Low IRQL(Bit3)
SR 1 Normal Operation
0
Overrun Error
Figure 15-5 Serial Method to Test Transmission
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16. BUZZER FUNCTION
The buzzer driver block consists of 6-bit binary counter, buzzer register, and clock source selector. It generates square-wave which has very wide range frequency (500Hz ~ 250kHz at fXIN= 4MHz) by user software. A 50% duty pulse can be output to R30/BUZ pin to use for piezoelectric buzzer drive. Pin R30 is assigned for output port of Buzzer driver by setting the bit 5 of PMR (address D9H) to "1". At this time, the pin R30 must be defined as output mode (the bit 0 of R3DD=1). Example: 2.4kHz output at 4MHz. LDM LDM SET1 CLR1
X means don't care
The bit 0 to 5 of BUR determines output frequency for buzzer driving. Equation of frequency calculation is shown below. f XIN f BUZ = --------------------------------------------------------------------------------------2 x DivideRatio x ( BUR [ 5:0 ] + 1 )
fBUZ: Buzzer frequency fXIN: Oscillator frequency Divide Ratio: Prescaler divide ratio by BUCK[1:0] BUR: Lower 6-bit value of BUR. Buzzer period value.
R3DD,#XXXX_XXX1B BUR,#0111_0011B PMR.5 PMR.5 ;BUZ ON ;BUZ OFF
The frequency of output signal is controlled by the buzzer control register BUR.The BUR[5:0] determine output frequency for buzzer driving.
BUR[7:6] SCMR[1:0] fXIN reserved Prescaler
0X 1X
/8 /16 /32 /64
00 01 10 11 MUX
R30 port data
6-bit Binary Counter /2 F/F Comparator 6-bit Compare Data BUR[5:0] [0FDH] 0 1 PMR.5
R30/BUZ PIN
Figure 16-1 Block Diagram of Buzzer Driver
ADDRESS: 0D9H RESET VALUE: 00H
R/W R/W R/W R/W R/W R/W R/W R/W
ADDRESS: 0FDH RESET VALUE: Undefined W W W W W W W W
PMR
-
-
BUZ EC2 EC0 INT2 INT1 INT0
BUR
BUCK1 BUCK0
R30/BUZ selection 0: R30 port (Turn off buzzer) 1: BUZ port (Turn on buzzer)
BUR[5:0] Define frequency of buzzer signal Source clock select 00: / 8 01: / 16 10: / 32 11: / 64
Figure 16-2 PMR and Buzzer Register
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Note that BUR is a write-only register. The 6-bit counter is cleared and starts the counting by writing signal at BUR register. It is incremental from 00H until it matches 6BUR [5:0] 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F BUCK[1:0] 00 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 01 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 10 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 11 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977
bit BUR value. When main-frequency is 4MHz, buzzer frequency is shown as below table. The unit is kHz. BUR [5:0] 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F BUCK[1:0] 00 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.906 01 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 10 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 11 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488
Table 16-1 Buzzer Frequency at 4MHz
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17. INTERRUPTS
The GMS81C7208/16 interrupt circuits consist of interrupt enable register (IENH, IENL), interrupt request flags of IRQH, IRQL, priority circuit, and master enable flag ("I" flag of PSW). twelve interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 17-2. The basic interval timer interrupt is generated by BITIF which is set by an overflow in the timer register. The watchdog timer interrupt is generated by WDTIF which set by a match in watchdog timer register. The external interrupts INT0 ~ INT2 each can be transition-activated (1-to-0 or 0-to-1 transition) by selection IEDS. The flags that actually generate these interrupts are bit INT0IF, INT1IF and INT2IF in register IRQH and IRQL. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The timer 0 ~ timer 3 interrupts are generated by T0IF~T3IF which are set by a match in their respective Timer/Counter register. The serial communication interrupts are generated by SIOIF which is set by 8-bit serial data transmitting or receiving through SCK, SIN, SOUT pin. The AD converter interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The watch timer interrupt is generated by WTIF which is set by an 14-bit binary counter overflow. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on page 18), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except power-on reset and software BRK interrupt. Below table shows the Interrupt priority. Reset/Interrupt Hardware Reset Reserved Basic Interval Timer Watchdog Timer External Interrupt 0 External Interrupt 1 Timer/Counter 0 Timer/Counter 1 External Interrupt 2 Serial Communication ADC Interrupt Watch Timer Interrupt Timer/Counter 2 Timer/Counter 3 Symbol RESET BIT WDT INT0 INT1 Timer 0 Timer 1 INT2 SCI ADC WT Timer 2 Timer 3 Priority 1 2 3 4 5 6 7 8 9 10 11 12 13
Vector addresses are shown in Figure 8-6 on page 20. Interrupt enable registers are shown in Figure 17-3. These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, Iflag, which disables all interrupts at once.
R/W
-
-
R/W
SIOIF
R/W
ADIF
R/W
WTIF
R/W T2IF
R/W T3IF LSB
IRQL
External Interrupt 2
INT2IF
MSB
ADDRESS: 0DCH INITIAL VALUE: 0--0 0000B
Serial Communication
Timer/Counter 3 Timer/Counter 2 Watch Timer A/D Converter
-
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W T1IF LSB
IRQH
MSB
-
BITIF WDTIF INT0IF INT1IF T0IF
ADDRESS: 0DDH INITIAL VALUE: -000 0000B
Timer/Counter 1 Interrupt Request Flag Timer/Counter 0 Basic Interval Timer Watchdog Timer External Interrupt 1 External Interrupt 0
Figure 17-1 Interrupt Request Flag
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.
Internal bus line I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.
[0DAH] IRQL [0DCH] INT2 Serial Communication A/D Converter Watch Timer Timer 2 Timer 3 IRQH [0DDH] BIT Watchdog Timer INT0 INT1 Timer 0 Timer 1 BITIF WDTIF INT0IF INT1IF T0IF T1IF INT2IF SIOIF ADIF WTIF
IENL
Interrupt Enable Register (Lower byte)
Release STOP
Priority Control
T2IF T3IF
To CPU I-flag Interrupt Master Enable Flag Interrupt Vector Address Generator
[0DBH]
IENH
Interrupt Enable Register (Higher byte)
Internal bus line
Figure 17-2 Block Diagram of Interrupt
R/W -
-
R/W
SIOE
R/W ADE
R/W WTE
R/W T2E
R/W T3E LSB
IENL
INT2E
MSB
ADDRESS: 0DAH INITIAL VALUE: 0--0 0000B Timer/Counter 3 Interrupt Enable Flag Timer/Counter 2 Interrupt Enable Flag Watch Timer Interrupt Enable Flag A/D Converter Interrupt Enable Flag Serial Communication Interrupt Enable Flag External Interrupt 2 Enable Flag
-
R/W
R/W
BITE
R/W
R/W
R/W
R/W T0E
R/W T1E LSB
IENH
MSB
-
WDTE INT0E INT1E
ADDRESS: 0DBH INITIAL VALUE: -000 0000B Timer/Counter 1 Interrupt Enable Flag Timer/Counter 0 Interrupt Enable Flag External Interrupt 1 Enable Flag External Interrupt 0 Enable Flag Watchdog Timer Interrupt Enable Flag Basic Interval Timer Interrupt Enable Flag
VALUE 0: Disable 1: Enable
Figure 17-3 Interrupt Enable Flag
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17.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fXIN (2 s at fMAIN=4.19MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI].
2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
Interrupt Acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled.
System clock Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 17-4 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
Watch Timer Vector Table Address
Entry Address
0FFE4H 0FFE5H
012H 0E3H
0E312H 0E313H
0EH 2EH
Saving/Restoring General Purpose Register
Correspondence between vector table address for Watch Timer Interrupt and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced.
During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers.
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Example: Register save using push and pop instructions INTxx: PUSH PUSH PUSH A X Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.
17.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the Iflag is cleared to disable any further interrupt. But as user sets Iflag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : LDM LDM POP POP POP RETI A X Y IENH,#08H IENL,#00H
interrupt processing
POP POP POP RETI
Y X A
;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN
General-purpose register save/restore using push and pop instructions;
main task acceptance of interrupt interrupt service task saving registers
;Enable INT0 only ;Disable other ;Enable Interrupt
restoring registers interrupt return
17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 17-5. .
IENH,#0FFH ;Enable all interrupts IENL,#0FFH Y X A
Main Program service
TIMER 1 service INT0 service
enable INT0 disable other EI Occur TIMER1 interrupt
Occur INT0
B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI
=0
TCALL0 ROUTINE
enable INT0 enable other
RET In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
Figure 17-5 Execution of BRK/TCALL0
Figure 17-6 Execution of Multi Interrupt
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17.4 External Interrupt
The external interrupt on INT0, INT1 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0D8H) as shown in Figure 17-7. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. : : ;**** Set port as an input port R00,R02 LDM R0DD,#1111_1010B ; ;**** Set port as an external interrupt port LDM PMR,#05H ; ;**** Set Falling-edge Detection LDM IEDS,#0001_0001B : :
INT0 pin
INT0IF INT0 INTERRUPT
Response Time
The INT0 ~ INT2 edge are latched into INT1IF ~ INT2IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 17-8 shows interrupt response timings.
INT1 pin
INT1IF INT1 INTERRUPT
INT2 pin
INT2IF INT2 INTERRUPT
2
2
2 Edge selection register max. 12 fXIN period 8 fXIN period
IEDS [0D8H]
Figure 17-7 External Interrupt Block Diagram INT0 ~ INT2 are multiplexed with general I/O ports (R00~R02). To use as an external interrupt pin, the bit of Port Mode Register PMR should be set to "1" correspondingly as shown in Figure 179. Example: To use as an INT0 and INT2
Interrupt Interrupt goes latched active Interrupt processing Interrupt routine
Figure 17-8 Interrupt Response Timing Diagram
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R/W
R/W -
R/W BUZ
R/W
R/W
R/W
R/W
R/W ADDRESS: 0D9H INITIAL VALUE: 00H
PMR
MSB
-
EC2S BTCL INT2S INT1S INT0S EC0S
LSB 0: R00 1: INT0 0: R01 1: INT1
0: R30 1: BUZ 0: R04 1: EC2 MSB LSB R/W
0: R02 1: INT2 0: R03 1: EC0
-
R/W
R/W
R/W
R/W
R/W
IEDS
-
BTCL IED2H IED2L IED1H IED1L IED0H IED0L INT2 INT1 INT0
ADDRESS: 0D8H INITIAL VALUE: 00H
Edge selection register 00: Reserved 01: Falling (1-to-0 Transition) 10: Rising (0-to-1 Transition) 11: Both (Rising & Falling)
Figure 17-9 PMR and IEDS Registers
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18. LCD DRIVER
The GMS81C7208/16 has the circuit that directly drives the liquid crystal display (LCD) and its control circuit. In addition, VCLn pin is provided as the drive power pin. GMS81C7208/16 1/4 Duty: 1/3 Duty: 1/2 Duty: Static: 17 SEG x 4COM 18 SEG x 3COM 19 SEG x 2COM 20 SEG x 1COM Basically, the GMS81C7208/16 has 17 seg.x 4 com. ports of LCD driver. Extend display modes are shown in left table. Figure 18-1shows the configuration of the LCD driver.
********Caution******** When you developing the software using by Emulator, you must select the external bias resistor mode because of no internal bias resistor inside the Emulator (EVA. chip).
Select SEG or Normal port by LPMR [0F2H] SEG0/R40
Display Data Select Control
Display Data Buffer register
R4 or Segment
SEG7/R47
Segment Driver
LPMR[1:0]
"Same with above"
Display Memory (27 x 4 bits)
SEG8/R50 SEG11/R53 SEG16/R60 SEG20/R64
LPMR[3:2]
"Same with above"
INTERNAL BUS LINE
LPMR[5:4] WTCK[1:0] LCD Timing Control / 32
00 01
Prescaler
fMAIN/27
/ 128 MUX / 256
Common Driver
COM. or SEG.
reserved
/ 64
COM0 COM1/SEG26 COM2/SEG25 COM3/SEG24
MUX
LCR[3:2] of address 0F1H Power & Bias control
Control frame frequency
LCR
Enable LCD Control bias voltage and resistor
BIAS VCL2 VCL1 VCL0
[0F1H]
Figure 18-1 LCD Driver Block Diagram
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18.1 LCD Control Registers
The LCD driver is controlled by the LCD control register LCR which is shown in Figure 18-2. LCD block input the clock from the watch timer. When LCD is operate, the watch timer much be enabled by WTEN (bit 6 of address 0EFH).
R/W 7
R/W 6
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0
LCR
SUBM BTC LCDEN BRC DTY1 DTY0 LCK1 LCK0
ADDRESS: 0F1H INITIAL VALUE: 00H Selection Frame Frequency 00: fXIN/27/32, 1024Hz@4.19MHz 01: fXIN/27/64, 512Hz@4.19MHz 10: fXIN/27/128, 256Hz@4.19MHz 11: fXIN/27/256, 128Hz@4.19MHz
Bias Transistor Control 0: Off 1: On LCD Display Control 0: LCD Display All Segment 0 Data Output 1: LCD Display Enable
Duty Control 00: 1/4 Duty 01: 1/3 Duty (SEG24 Active) 10: 1/2 Duty (SEG24, SEG25 Active) 11: Static (SEG24, SEG25, SEG26 Active) Bias Resistor Control 0: External 1: Internal No internal bias registers in the Emulator, so user must select the "0", External mode at least during use the Emulator. OTP and Mask MCU can use both. R/W R/W 1 0 R4LPMR
** Caution : The bit7(SUBM) of LCR register must be set to "1" by software because of reduction current consumption (reset value="0").
LPMR
R/W 7 -
R/W 6 -
R/W R/W 5 4 R6LPMR
R/W R/W 3 2 R5LPMR
ADDRESS: 0F2H INITIAL VALUE:0000 0000
R4 port Selection 00:SEG0~SEG7 01:SEG4~SEG7,R40~R43 10:SEG0~SEG3,R44~R47 11:R40~R47 R5 port Selection 00:SEG8~SEG11 01:R50~R53 10:SEG8~SEG11 11:R50~R53 R6 port Selection 00:SEG16~SEG20 01:SEG20,R60~R63 10:SEG16~SEG19,R64 11:R60~R64 7
6
5
4
3
R/W
2 1
R/W
0
RPR
-
-
-
-
-
-
RPR1 RPR0
ADDRESS: 0F3H INITIAL VALUE: 00H
The RPR register is used for RAM page selection. RAM page Page 0 Page 0 Page 1 Reserved Reserved Instruction CLRG SETG SETG SETG SETG PRP1 X 0 0 1 1 PRR0 X 0 1 0 1
Figure 18-2 LCD Control Register
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18.2 Duty and Bias Selection of LCD Driver
5 kinds of driving methods can be selected by DTY (bits 3 and 2 of LCD Control Register and connection of VCL pin externally. Figure 18-3 shows typical driving waveforms for LCD.).
VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2
1/fF
Data "1"
Data "0"
VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2
1/fF
Data "1"
Data "0"
(a) 1/4 duty, 1/3 bias
VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2 1/fF VCL2 VCL1 = VCL0 GND -VCL0 = -VCL1 -VCL2 Data "1" Data "0"
(b) 1/3 duty, 1/3 bias
1/fF
Data "1" Data "0"
(c) 1/2 duty,1/3 bias
VCL2 VCL1 VCL0 GND -VCL0 -VCL1 -VCL2 1/fF
(d) 1/2 duty, 1/2 bias
Note: fF: LCD Frame Frequency
Data "1"
Data "0"
(e) Static
Figure 18-3 LCD Drive Waveform (Voltage COM-SEG Pins)
18.3 Selecting Frame Frequency
Frame frequency is set to the main frequency as shown in the following Table 18-1. The LCK[1:0] of LCR determines the frequency of COM signal scanning of each segment output. The watch timer must be enabled when the LCD display is turned on. RESET clears the LCD control register LCR values to logic zero. The LCD display can continue to operate even during the SLEEP and STOP modes. . LCK[1:0] 00 01 10 11 LCD clock fXIN/27/32 fXIN/27/64 fXIN/27/128 fXIN/27/256 Frame Frequency (Hz)
(When fXIN = 4.19 MHz)
1024 512 256 128
Table 18-1 Setting of LCD Frame Frequency
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COM0 pin
one frame (at 1/4 duty, 1/3 bias)
LCD Port Selection
Segment pins are also used for normal I/O pins. The LCD port selection register LPMR is used to set Rn pin for ordinary digital input. Refer to LPMR register as shown in Figure 18-2.
Bias Resistor
To operate LCD, built-in Bias resistor dividing VDD to VSS section into several stages generates necessary voltage.
The BTC (Bit 6 of LCR) switches Transistor supplying voltage to serially connected Bias resistor. If it is `1', it turns on, and if it is `0', it turns off. The LCD drive voltage (VCL2) is given by the difference in potential (VDD-VCL2) between pins VDD and VCL2. Therefore, when the MCU operating voltage is 5V and LCD drive voltage are the same, the Bias pin is connected to the VCL2 pin as shown in (a) of Figure 18-5.
MCU Internal
BTC
VDD
MCU Internal
BTC
VDD
2R Internal Bias resistors
BIAS
2R Internal Bias resistors Two pins are connected each other VCL2=5V VCL1=3.33V VCL0=1.67V
BIAS
R
VCL2
R
VCL2
Short two pins each other externally VCL2=5V VCL1=2.5V VCL0=2.5V
R
VCL1
R
VCL1
R VSS BRC
VCL0
R VSS BRC
VCL0
BTC = "1"
BRC = "1"
BTC = "1"
BRC = "1"
Typ. R=65k
(a) Internal, Static or 1/3 Bias
(b) Internal, Static or 1/2 Bias
Figure 18-4 Application Example of 5V LCD Panel When require supply 3V output to the LCD, the voltage of VCL2 becomes 3V as shown in Figure 18-5. Because VDD is down to 3V through internal 2R resistor. The LCD light only when the difference in potential between the segment and common output is VCL, and turn off at all other times. During reset, the power switch of the LCD driver is turned off automatically, shutting off the VCL voltage.
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MCU Internal
BTC
VDD = 5V
MCU Internal
BTC
VDD = 5V
2R Internal Bias resistors Typ. R=65k
BIAS
R
VCL2
Internal Bias resistors
VCL2=3V VCL1=2V VCL0=1V
2R
BIAS
VCL2=3V VCL1=1.5V VCL0=1.5V
R
VCL2
R
VCL1
R
VCL1
Short two pins externally
R VSS BRC
VCL0
R VSS BRC
VCL0
BTC = "1"
BRC = "1"
BTC = "1"
BRC = "1"
Typ. R=65k
(a) Internal, Static or 1/3 Bias
(b) Internal, Static or 1/2 Bias
Figure 18-5 Application Example of 3V LCD Panel Some user want to use external bias resister instead of internal, you can connect external resistor as shown in Figure 18-6. And the external capacitors are may required for stable display according to your system environment.
MCU Internal
BTC
VDD
BTC = "0"
2R Internal Bias resistors BIAS
VDD Adjust Contrast
R
VCL2
R
VCL1
R
VCL0 VSS External circuit
BRC = "0"
BRC
VSS
Figure 18-6 External Resistor
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18.4 LCD Display Memory
Display data are stored to the display data area (address 100H-11AH) in the data memory. The display data stored to the display data area are read automatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the display data and drive method.
Bit 0 SEG26 SEG25 SEG24
1
2
3
4
5
6
7 11AH 119H 118H
SEG20 SEG19 SEG18 SEG17 Note: The bit 4 to 7 of every byte are reserved. Any read or write is not effect. SEG16
-
-
-
-
-
-
-
117H 116H 115H 114H 113H 112H 111H 110H
SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
-
-
-
-
-
-
-
10FH 10EH 10DH 10CH 10BH 10AH 109H 108H 107H 106H 105H 104H 103H 102H 101H 100H
COM0
COM1
COM2
Figure 18-7 LCD Display Memory
COM3
Therefore, display patterns can be changed by only overwriting the contents of the display data area with a program. The table look up instruction is mainly used for this overwriting. Figure 18-7 shows the correspondence between the display data area and the SEG/COM pins. The LCD lights when the display data is "1" and turn off when "0". The number of segment which can be driven differs depending on the LCD drive method, therefore, the number of display data area bits used to store the data also differs
(Refer to Figure 18-2). Consequently, data memory not
Drive Methods 1/4 Duty 1/3 Duty 1/2 Duty Static Bit 3 COM3 Bit 2 COM2 COM2 Bit 1 COM1 COM1 COM1 Bit 0 COM0 COM0 COM0 COM0
Table 18-2 The Duty vs. COM Port Configuration
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used to store display data and data memory for which the address are not connected to LCD can be used to store ordinary user's processing data. Blanking
Blanking is applied by setting LCDEN (bit 7 of LCR) to "0" and
turns off the LCD by outputting the non light operation level to the COM pin. When setting Frame frequency or changing operating mode, LCD display should be off before operation, to prevent display flickering.
18.5 Control Method of LCD Driver
Initial Setting Flow chart of initial setting is shown in Figure 18-8. Example: When operating with 1/4 duty LCD using a
Select Frame Frequency
frame frequency of 512Hz.
LDM : SETG LDM
LCR,#0101_0001B;1/4duty, fF=512Hz (fSUB= 32.768kHz) RPR,#1;Select LCD Memory ;area (Page 1 = address 1XXH) #0 #0 ;RAM Clear ;RAM(100H~11AH) {X}+ #01BH C_LCD1
Clear LCD Display Memory
LDX C_LCD1: LDA STA CMPX BNE CLRG : : SET1 : :
Turn on LCD
LCR.5;Enable LCD display
.
COM0 COM1 Setting of LCD drive method SEG0 Initialize of display memory SEG1 Example: display "2" Enable display (Release of blanking)
bit 7 6 5 4 3 2 1 0
COM2 COM3
100H 101H
* *
* *
* *
* *
0 1
0 1
1 1
1 0
Note: * are don't care.
Figure 18-8 Initial Setting of LCD Driver
Figure 18-9 Example of Connection COM & SEG
Display Data Setting Normally, display data are kept permanently in the program memory and then stored at the display data area by the table look-up instruction. This can be explained using numerical display with 1/4 duty LCD as an example. The COM and SEG connections to the LCD and display data are the same as those shown is Figure 18-9. Programming
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example for displaying character is shown below.
: CLRG LDX#DISPRAM LDA{X} TAY LDA!FONT+Y ;LOAD FONT DATA LDMRPR,#1;Set RPR = 1 to access LCD SETG ;Set Page 1 LDX#0 STA{X}+;LOWER 4 BITS OF ACC. -> M(X) XCN STA{X} ;UPPER 4 BITS OF ACC. -> M(X+1) CLRG ;Set Page = 0 : :
GOLCD: Write into the LCD Memory
Font data
FONT
DB DB DB DB DB DB DB DB DB DB
1101_0111B; 0000_0110B; 1110_0011B; 1010_0111B; 0011_0110B; 1011_0101B; 1111_0101B; 0000_0111B; 1111_0111B; 0011_0111B;
"0" "1" "2" "3" "4" "5" "6" "7" "8" "9"
Note: When power on RESET, an oscillation start up time is required. Enable LCD display after an oscillation is stabilized, or LCD may occur flicker at power on time shortly.
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19. WATCH / WATCHDOG TIMER
19.1 Watch Timer
The watch timer goes the clock continuously even during the power saving mode. When MCU is in the Stop or Sleep mode, MCU can wake up itself every 2Hz or 4Hz or 16Hz. The watch timer consists of input clock selector, 14-bit binary counter, interval selector and watch timer mode register WTMR (address 0EFH). The WTMR is 5-bit read/write register and shown in Figure 19-2. WTMR can select the clock input by 2 bits WTCK[1:0] and interval time selector by 2 bits WTIN[1:0] and enable/disable bit. The WTEN bit is set to "1" timer start counting. Input clocks can be selected among three different source which are divided main clock (fXIN /128) or main clock. Recommend the oscillator 4.194304MHz as a main. Because above main frequency is equal to 128 times of 32.768kHz. Generally main clock (fXIN) at WTCK=10B is not be used, it is just for test purpose in factory. In the Stop Mode, the main clock is stopped. LDM EI LDM IENL,#XXXX_X1XXB WTMR,#0100_1000B
WDCK[1:0] MUX 10 11 16Hz 8Hz
WDCLR
0: Stop 1: Clear and start clear
00 2Hz WTCK[1:0] reserved fXIN /128 fXIN(test)
01 4Hz
2-bit Binary Counter
to RESET CPU
0 overflow 1 enable WDEN Watchdog Timer Interrupt
00 01 10
0f W 1 enable WTEN
14-bit Binary Counter 16Hz 2Hz 4Hz
WDTIF WDOM
When fXIN = 4.194304 MHz
10 01 00 Interval Selector MUX WTIN[1:0]
WTIF
Watch Timer interrupt
Figure 19-1 Block Diagram of Watchdog Timer
19.2 Watchdog Timer
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request as you want. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. Clearing the 2-bit binary counter by bit WDCLR of WDTR is repeated within the detection time. If the malfunction occurs for any cause, the watchdog timer output will become active from the binary counters unless the binary counter is cleared. At this time, when WDOM=1, a reset is generated, which drives the RESET pin to low to reset the internal hardware. When WDOM=0, a watchdog timer interrupt (WDTIF) is generated instead of Reset function. This interrupt can be used general timer as user want. When main clock is selected as clock input source on the STOP mode, clock input is stopped so the watchdog timer temporarily stops counting.
Watchdog Timer Control
Figure 19-2 shows the watchdog timer control register WDTR (address 0DFH). The watchdog timer is automatically enabled initially and watchdog output to reset CPU but clock input source is disabled. To enable this function, you should write bit WTEN of WTMR (address 0EFH) set to "1".
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-
R/W
WTEN
-
-
R/W
R/W
R/W
R/W
WTMR
-
WTIN1 WTIN0 WTCK1 WTCK0
ADDRESS: 0EFH INITIAL VALUE: -0--_0000B
Watch Timer Count Enable 0: Disable 1: Enable
Clock Source Selection 00: Reserved 01: Main Clock (fXIN / 128) 10: Main Clock (test purpose in factory) 11: Watch Timer Interrupt Interval Selection 00: 16Hz When 01: 4Hz fXIN = 4.19MHz 10: 2Hz 11: -
-
-
R/W
-
R/W
R/W
R/W
R/W
R/W
WDTR
-
WDEN WDCK1 WDCK0 WDOM WDCLR
ADDRESS: 0DFH INITIAL VALUE: --01_0010B Clear Bit 0: Normal operation 1: Clear and starts counting
Watchdog Timer Count Enable 0: Disable 1: Enable
Output Mode 0: Interrupt Request 1: Reset CPU Watchdog Timer Interrupt Interval Selection 00: 2 sec. When 01: 1 sec. fXIN = 4.19MHz 10: 0.5 sec. 11: 0.25 sec.
Figure 19-2 WTMR, WDTR: Watch Timer and Watchdog Timer Data Register Example: Sets the Watchdog Timer Detection Time to 1 SEC at 4.19MHz LDM LDM WTMR,#0100_1000B;Select sub clock as an input source WDTR,#0001_0111B ;Clear counter
SET1 WDCLR : : Within 0.75 sec. : : SET1 WDCLR : : Within 0.75 sec. : : SET1 WDCLR
;Clear counter
;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDEN (bit 4 in CKCTLR) to "1". WDEN is initialized to "1" during reset and it should be clear to "0" disable. Example: Enables watchdog timer for Reset : LDM LDM : WTMR,#0100_XXXXB;WTEN 1 WDTR,#00X1_XX11B;WDEN 1
The watchdog timer is disabled by clearing either bit 4 (WDEN) of WDTR or bit 6 (WTEN) of WTMR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released.
Clearing 2-Bit Binary Counter of the Watchdog Timer
The watchdog timer count the clock source as 14-bit binary
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counter which is free run can not be cleared. The watchdog timer has 2-bit binary counter. It is incremented by 14-bit binary counter match as shown in Figure 19-1. Interrupt request flag or Reset signal are generated by overflow 2-bit binary counter. During normal operation in the software, 2-bit binary counter
should be cleared by bit WDCLR of WDTR within watchdog timer overflow. The time of clearing must be within 3 times of 14-bit binary counter interval as shown in Figure 19-3. The worst case, watchdog time is just 3 times of 14-bit counter.
1FFE
1FFF 0 1 2
1FFE
1FFF 0 1 2
1FFE
1FFF 0 1 2
1FFE
1FFF 0 1 2
~ ~
~ ~
~ ~
14-bit binary counter 2-bit binary counter
~ ~
~ ~
~ ~
n
0
1
2
3
0 Counter Clear
WDTIF interrupt
Even if user set to 1 sec., worst case 0.75 second Write WDCLR = 1 at this point
When WDTR = 0011_0111B
Figure 19-3 Watchdog Timer Timing If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. The main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode.
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20. POWER DOWN OPERATION
The GMS81C7208/16 has two power-down modes. In powerdown mode, power consumption is reduced considerably that in Battery operation Battery life can be extended a lot.
Sleep mode is entered by setting bit 0 of sleep mode register, and STOP mode is entered by STOP instruction.
20.1 SLEEP Mode
In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operate normally but CPU stops. Movement of all Peripherals is shown in Table 20-1. Sleep mode is entered by setting bit 0 of SMR (address 0DEH). It is released by RESET or interrupt. To be release by interrupt, interrupt should be enabled before Sleep mode.
Sleep Mode Register SMR 0: Release Sleep Mode 1: Enter Sleep Mode ADDRESS : 0DEH RESET VALUE : -------0 W
Figure 20-1 SLEEP Mode Register
Oscillator (XIN pin) Internal CPU Clock
~ ~ ~ ~
Interrupt
Set bit 0 of SMR Release
Normal Operation
Stand-by Mode
Normal Operation
Figure 20-2 Sleep Mode Release Timing by External Interrupt
.
Oscillator (XIN pin) Internal CPU Clock
~ ~ ~ ~
~ ~ ~~ ~~
RESET
Set bit 0 of SMR
Release
~~ ~~
~~ ~~
BIT Counter
0
1
2
FE
FF
0
1
2
Clear & Start
Normal Operation
Sleep Mode
tST = 62.5ms Normal Operation at 4.19MHz by hardware tST = 1 fMAIN /1024 x 256
Figure 20-3 SLEEP Mode Release Timing by RESET Pin
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20.2 STOP Mode
For applications where power consumption is a critical factor, device provides reduced power of STOP. Start the Stop Operation An instruction that STOP causes to be the last instruction is executed before going into the STOP mode. In the Stop
Peripheral CPU RAM LCD Driver Basic Interval Timer Timer/Event Counter Watch Timer Main-oscillation Sub-oscillation I/O Ports Control Registers Release Method STOP Mode All CPU operations are disabled Retain LCD driver operates continuously Halted Halted (Only when the Event counter mode is enabled, Timer operates normally) Watch Timer operates continuously Stop (XIN pin = "L", XOUT pin = "L") Oscillation Retain Retain RESET, SIO interrupt, Watch Timer interrupt, Timer interrupt (EC0,2), External interrupt
mode, the on-chip main-frequency oscillator is stopped. With the clock frozen, all functions are stopped, but the onchip RAM and Control registers are held. The port pins output the values held by their respective port data register, the port direction registers. The status of peripherals during Stop mode is shown below.
SLEEP Mode All CPU operations are disabled Retain LCD driver operates continuously BIT operates continuously Timer/Event Counter operates continuously Watch Timer operates continuously Oscillation Oscillation Retain Retain RESET, All interrupts
Table 20-1 Peripheral Operation During Power Down Mode Note: Since the XIN pin is connected internally to GND to avoid current leakage due to the crystal oscillator in STOP mode, do not use STOP instruction when an external clock is used as the main system clock. In the Stop mode of operation, VDD can be reduced to minimize power consumption. Be careful, however, that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. And after STOP instruction, at least two or more NOP instruction should be written as shown in example below. : The interval timer register CKCTLR should be initialized (0FH or 0EH) by software in order that oscillation stabilization time should be longer than 20ms before STOP mode.
Release the STOP Mode
The exit from STOP mode is using hardware reset or external interrupt, watch timer, key scan or Timer/Counter. To release STOP mode, corresponding interrupt should be enabled before STOP mode. Specially as a clock source of Timer/Event Counter, EC0 or EC2 pin can release it by Timer/Event Counter interrupt request. Reset redefines all the control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. Start-up is performed to acquire the time for stabilizing oscillation. During the start-up, the internal operations are all stopped.
Example)
; LDM LDM STOP NOP NOP CKCTLR,#0EBH;32.8ms CKCTLR,#0FBH ;65.5ms
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Oscillator (XIN pin) Internal Clock External Interrupt
~~ ~~
STOP Instruction Executed
~ ~ ~ ~ ~ ~ ~~ ~~
~ ~ ~ ~ ~~ ~~
BIT Counter
n
n+1 n+2
n+3
0 Clear
1
FE
FF
0
1
2
Normal Operation
Stop Operation
tST > 20ms by software
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms.
Figure 20-4 STOP Mode Release Timing by External Interrupt
Oscillator (XIN pin) Internal Clock
~~ ~~
~ ~ ~ ~
~ ~ ~ ~
RESET BIT Counter
~ ~
STOP Instruction Executed n n+1 n+2 n+2 n+3
~~ ~~
Normal Operation
Stop Operation tST > 62.5ms at 4.19MHz by hardware 1 fMAIN /1024
Figure 20-5 STOP Mode Release Timing by RESET
~~ ~~
0 Clear
1
FE
FF
0
1
2
Normal Operation
tST =
x 256
Minimizing Current Consumption The stop mode is designed to reduce power consumption. To minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
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It should be set properly that current flow through port doesn't exist. First consider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if un-firmed voltage level (not VSS or
VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low.
VDD INPUT PIN internal pull-up INPUT PIN VDD VDD i=0 OPEN
VDD
O
i GND VDD
O
i
Very weak current flows
X
Weak pull-up current flows
X
OPEN
i=0
GND
O
O
When port is configure as an input, input level should be closed to 0V or 5V to avoid power consumption.
Figure 20-6 Application Example of Unused Input Port
OUTPUT PIN ON OPEN ON OFF i GND VDD ON OFF OFF
OUTPUT PIN VDD L ON OFF i GND OFF ON i=0 GND L VDD
O
X
X O
O
In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port .
In the left case, much current flows from port to GND.
Figure 20-7 Application Example of Unused Output Port
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21. OSCILLATOR CIRCUIT
The GMS81C7208/16 has two oscillation circuits internally. XIN and XOUT are input and output for main frequency and SXIN and SXOUT are input and output for sub frequency, respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 21-1. To use RC oscillation instead of crystal, user should check mark on the "MASK ORDER & VERIFICATION SHEET" of the appendix of this manual. However in the OTP device, when the programming RC oscillation can be selected or not into the configuration bit. For
C1 XOUT C2 4.19MHz
more detail, refer to "24.1 OTP Programming" on page 84. Note: When using the sub clock oscillation, connect a resistor in series with R which is shown as below figure. In order to reduce the power consumption, the sub clock oscillator employs a low amplification factor circuit. Because of this, the sub clock oscillator is more sensitive to noise than the main system clock oscillator.
XIN VSS
Recommend Crystal Oscillator Ceramic Resonator C1,C2 = 20pF C1,C2 = 30pF
Crystal or ceramic oscillator
Open
XOUT REXT
XOUT For selection R value, Refer to AC Characteristics
External Clock
XIN
XIN
External Oscillator
RC Oscillator (mask option)
Figure 21-1 Oscillation Circuit Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 21-2 for the layout of the crystal. Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
XOUT XIN
Figure 21-2 Recommend Layout of Oscillator PCB Circuit
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22. RESET
The GMS81C7208/16 has two types of reset generation procedures; one is an external reset input, the other is a watch-dog timer reset. Table 22-1 shows on-chip hardware initialization by reset action.
VCC
On-chip Hardware Program Counter (PC) G-Flag (G) Operation Mode Peripheral Clock
Initial Value (FFFFH) - (FFFEH) 0 Main Operating Mode On Disable (Because the Watch timer is disabled) Refer to Table 8-1 on page 24 Enable
10k 7036P
+
Watchdog Timer
to the RESET pin
10uF
Control Registers Low Voltage Detector
Table 22-1 Initializing Internal Status by Reset Action Figure 22-1 Simple Power-On Reset Circuit.
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2. Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should
1 2 3 4 5 6 7
be initialized before read or tested it. When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure .
~ ~
Oscillator (XIN pin) RESET
~ ~ ~ ~
ADDRESS BUS DATA BUS
?
?
?
?
FFFE FFFF Start
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time tST = 62.5mS at 4.19MHz
Figure 22-2 Timing Diagram after RESET
~ ~
RESET Process Step tST = 1 fMAIN /1024 x 256 MAIN PROGRAM
22.2 Watchdog Timer Reset
Refer to "18. LCD DRIVER" on page 65.
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23. POWER FAIL PROCESSOR
The GMS81C7208/16 has an on-chip low voltage detection circuitry to detect the VDD voltage. A configuration register, LVDR (address 0FBH), can enable or disable the low voltage detect circuitry. Whenever VDD falls close to or below 2.2V, the LVD0 is just set to "1", and if it recovering 3.4V, LVD0 is held to "1". If VDD falls below around 3.4V range, the low voltage situation may reset the MCU or freeze the clock according to setting of bit 5 (LVDM) of LVDR . The bit 4 LVD1 function is same with LVD0 except different voltage level 2.1V. The detection voltage is varied very little. See "7.3 DC Electrical Characteristics" on page 10 for more detail voltage level. In the in-circuit emulator, power fail function is not implemented and user may not use it. Therefore, after completed development of user program, this function may be experimented or evaluated using by OTP. When power fail certainly occur the MCU was reset, program notify this Reset circumstance cause by LVD function. So, does not erase the all RAM contents and operates subsequently as shown in Figure .
ADDRESS: 0FBH INITIAL VALUE: 00H 3
LVD0
R/W 7
R/W 6
LVDS
R/W 5
LVDM
R/W 4
LVD1
2
1
0
LVDR
LVDE
VDD Detection Flag 1 0: Above 3.4V 1: Below 3.4V VDD Detection Flag 2 0: Above 2.1V 1: Below 2.1V Operation Mode 0: Clock freeze 1: Reset Power Fail Voltage Selection 0: 3.4V 1: 2.1V Enable / Disable flag 0: Disable 1: Enable
Figure 23-1 Low Voltage Detector Register
RESET VECTOR
LVD0 =1 NO RAM CLEAR INITIALIZE RAM DATA
YES
Skip the initial routine when the Reset cause from power fail.
INITIALIZE ALL PORTS INITIALIZE REGISTERS
FUNTION EXECUTION
Figure 23-2 S/W Example for RESET by Power Fail
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VDD Internal RESET VDD When LVDM = 1 Internal RESET VDD Internal RESET 64mS t <64mS 64mS 64mS
LVDVDDMAX LVDVDDMIN
LVDVDDMAX LVDVDDMIN
LVDVDDMAX LVDVDDMIN
Figure 23-3 Power Fail Processor Situations
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24. DEVELOPMENT TOOLS
24.1 OTP Programming
The GMS87C7216 is OTP (One Time Programmable) type microcontrollers. Its internal user memory is constructed with EPROM (Electrically programmable read only memory). The OTP microcontroller is generally used for chip evaluation, first production, small amount production, fast mass production, etc. Blank OTP's internal EPROM is filled by 00H, not FFH. Note: In any case, you have to use the *.OTP file for programming, not the *.HEX file. After assemble the source program, both OTP and HEX file are generated by automatically. The HEX file is used during program emulation on the emulator.
87C71XX-52SD
87C70XX-64SD
87C70XX-64QF
How to Program
To program the OTP devices, user should use MagnaChip own programmer. Ask to MagnaChip sales part for purchasing or more detail.
87C70XX-64SD
Programmer:
87C71XX-52SD
CHOICE-SIGMA (Single type) PGM-Plus (Single type) StandAlone-GANG4 (4-gang type)
87C70XX-64QF
Socket adapter:87C70XX-64SD (for 64SDIP) 87C70XX-64QF (for 64MQFP) 87C70XX-64LQ (for 64LQFP) The CHOICE-SIGMA is a MagnaChip universal single programmer for all of MagnaChip OTP devices, also the StandAloneGANG4 can program four OTPs at once.
Programming Procedure 1. Select device GMS87C7216 as you want. 2. Load the *.OTP file from the PC to programmer. The file is composed of Motorola-S1 format. 3. Set the programming address range as below table. 4. Mount the socket adapter on the programmer. 5. Set the configuration bytes as your needs. 6. Start program/verify. Select the Options for Program Lock and RC Oscillation
Except the user program memory C000H~FFFFH, there is configuration byte (address 707FH) for the selection of program lock and RC oscillation. The configuration byte of OTP is shown as Figure 24-1. It could be served when user use the OTP program-
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mer (PGM-Plus, Choice-Sigma or StandAlone-Gang4).
Figure 24-1 The OTP Configuration Byte
OTP Configuration Byte
7 6 5 4 3
ADDRESS: 707FH 2
LOCK
1
RC
0
Oscillation Option 0: Crystal or Resonator 1: External RC Oscillator Lock bit 0: Allow Code Read Out 1: Not Allow Code Read Out
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J_USERB
SEG46 SEG44 SEG42 SEG40 SEG38 VREG COM1/S36 COM3/S34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 SEG4 SEG2 SEG0
J_USERA
GND SEG47 VCL0 SEG45 VCL2 SEG43 CA SEG41 GND SEG39 /U_RST SEG37 U_XOUT COM0 GND COM2/S35 R37 SEG33 R35 SEG31 R20 SEG29 R22 SEG27 R24 SEG25 R26 SEG23 R17 SEG21 R15 SEG19 R13 SEG17 R11 SEG15 R07 SEG13 R05 SEG11 R03 SEG9 R01 SEG7 R33 SEG5 R31 SEG3 +5V SEG1
RUN
STOP
SLEEP
24.2 Emulator EVA. Board Setting
VR1
POWER
SW2
External oscillator SW1 socket +5V
XOUT OFF ON
J_USERB J_USERA
X1 (OSC)
V_USER
GMS81C7208/7216
Supply +5V (max. 200mA)
21
RESET
X2
/RESET
GND VCL1 VLCDC CB GND N.C. REMOUT (TONED) GND R36 R34 R21 R23 R25 R27 R16 R14 R12 R10 R06 R04 R02 R00 R32 R30 +5V
CHOICE-Dr. EVA 81C51/81C7x B/D Rev 1.1 S/N. ---------------
1 2 3 4 5 6 7 8
SW4
1 2
SW5
LCD_Vdd
VLCDC
OFF
ON
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DIP Switch and VR Setting
Before execute the user program, keep in your mind the below configuration DIP S/W, VR SW1 Description Emulator Reset Switch. Reset the Emulator. ON/OFF Setting Reset the Emulator. Normally OFF. EVA. chip can be reset by external user target board. ON : Reset is available by either user target system board or Emulator RESET switch. OFF : Reset the MCU by Emulator RESET switch. Does not work from user target board. Normally OFF. MCU XOUT pin is disconnected internally in the Emulator. Some circumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit
SW2-1
1
EVA. Chip
RESET pin
Pod RESET pin configuration SW2
SW2-2
2
EVA. Chip Oscillator
XOUT pin
Pod XOUT pin configuration External Bias Resistors Connection
EVA. Chip Internal
BIAS
VDD
SW4
SW4-1
Adjust Contrast VR1 50k
1 2 3
VCL2
SW4-2
VCL1
10k x 3 SW4-3
VCL0
Must be ON position. It serves the external bias resistors. If this switches are turned off, LCD bias voltage does not supplied, floated because there are no internal bias resistors and bias Tr. inside the Emulator.
0.47uF x 3
VSS
External Resistor and Capacitor
SW4
4 5 6
LCD Voltage doubling circuit.
Must be OFF position. It is reserved for the GMS81C5108. Must be ON position. This switch select the Stack page 0 (off) or page 1 (on). ON : For the 81C7XXX OFF : For the GMS81C5108
VDD SW4-8
7
Select the Stack Page.
EVA. Chip
LVD pin
8 81Cx detect the VDD voltage but Emulator can not do because Emulator can not operate if VDD is below normal opr. voltage (5V), This switch serves LVD environment through the applying 0V to LVD pin of EVA. chip during 5V normal operation.
Position ON during normal operation. ON : Normal operation OFF : Force to detect the LVD, refer to "23. POWER FAIL PROCESSOR" on page 82.
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DIP S/W, VR SW5 1 2
Description Internal power supply to sub-oscillation circuit. Reserved for other purpose. Adjust the LCD contrast. It supply bias voltage and adjust the VCL2 voltage.
EVA. Chip Internal
BIAS
ON/OFF Setting Must be ON position. Must be OFF position.
VDD
Adjust Contrast
VR1 50k
SW4-1
VCL2
VR1
-
SW4-2
VCL1
10k x 3 SW4-3
Adjust the proper position as well as LCD display good.
VCL0
0.47uF x 3
VSS
External Resistor and Capacitor
VR2
-
Reserved for other purpose.
Don't care.
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APPENDIX
A. MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET
GMS81C7208 GMS81C7216 -LA
Customer should write inside thick line box. 1. Customer Information Company Name Application Order Date Tel: E-mail: Name & Signature: 3. Marking Specification
08 or 16 YYYY MM DD
6~
2. Device Information Package ROM Size
RC OSC Opt.
44MQFP 8K Crystal
44LQFP 16K RC .OTP) )
GMS81C7216 (16K ROM) GMS81C7208 (8K ROM)
Fax:
Mask Data File Name: ( Check Sum: ( .OTP file data Internet C000H
DFFFH E000H
(Please check mark into
)
FFFFH
GMS81C72 YYWW
-LA
Customer's logo
MagnaChip ROM Code Number
KOREA
-LA GMS81C72 YYWW KOREA
Customer logo is not required. If the customer logo must be used in the special mark, please submit a clean original of the logo. Customer's part number
Lot Number
4. Delivery Schedule
Date
YYYY MM DD
Quantity
MagnaChip Confirmation
Customer Sample
YYYY MM DD
pcs pcs This box is written after "5.Verification".
Risk Order
5. ROM Code Verification Verification Date:
YYYY MM DD
Approval Date:
YYYY
MM
DD
Please confirm our verification data.
I agree with your verification data and confirm you to make mask set.
Check Sum: Tel: E-mail: Name & Signature:
01-AUG-2003
Tel: Fax: Name & Signature:
Fax:
GMS81C7208/7216
B. INSTRUCTION
B.1 Terminology List
Terminology A X Y PSW #imm dp !abs [] {} { }+ .bit A.bit dp.bit M.bit rel upage n + x Accumulator X - register Y - register Program Status Word 8-bit Immediate Data Direct Page Offset Address Absolute Address Indirect Expression Register Indirect Expression Register Indirect Expression, after that, Register Auto-Increment Bit Position Bit Position of Accumulator Bit Position of Direct Page Memory Bit Position of Memory Data (000H~0FFFH) Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address Table CALL Number (0~15) Addition
0 Bit Position
Description
Upper Nibble Expression in Opcode
y - x / ()
1 Bit Position
Upper Nibble Expression in Opcode
Subtraction Multiplication Division Contents Expression AND OR Exclusive OR NOT Assignment / Transfer / Shift Left Shift Right Exchange Equal Not Equal
~ =
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B.2 Instruction Map
LOW HIGH
00000 00 -
00001 01 SET1 dp.bit
00010 02 BBS A.bit,r el
00011 03 BBS dp.bit, rel
00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#i mm
00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp
00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X
00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs
01000 08 ASL A ROL A LSR A ROR A INC A DEC A
01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp
01010 0A TCAL L 0 TCAL L 2 TCAL L 4 TCAL L 6 TCAL L 8 TCAL L 10 TCAL L 12 TCAL L 14
01011 0B SETA 1 .bit CLRA 1 .bit NOT1 M.bit OR1 OR1B AND1 AND1 B EOR1 EOR1 B LDC LDCB STC M.bit
01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp
01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y
01110 0E PUSH A PUSH X PUSH Y PUSH PSW
01111 0F BRK
000
001
CLRC
BRA rel PCAL L Upage RET
010
CLRG
011
DI
100
CLRV
TXSP
INC X DEC X
101
SETC
TSPX
110
SETG
TXA
XCN
DAS
111
EI
TAX
XAX
STOP
LOW HIGH
10000 10 BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel
10001 11 CLR1
dp.bit
10010 12 BBC
10011 13
dp.bit,r el
10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X}
10101 15 ADC !abs+ Y SBC !abs+ Y CMP !abs+ Y OR !abs+ Y AND !abs+ Y EOR !abs+ Y LDA !abs+ Y STA !abs+ Y
10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X]
10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y
11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs
11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X
11010 1A TCAL L 1 TCAL L 3 TCAL L 5 TCAL L 7 TCAL L 9 TCAL L 11 TCAL L 13 TCAL L 15
11011 1B JMP !abs CALL !abs
11100 1C BIT !abs TEST !abs TCLR 1 !abs CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs
11101 1D ADD W dp SUB W dp CMP W dp LDYA dp INCW dp DEC W dp STYA dp CBNE dp
11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y
11111 1F JMP [!abs] JMP [dp] CALL [dp]
000
BBC
A.bit,rel
001
010
MUL
011
DBNE Y
RETI
100
DIV
TAY
101
XMA {X} LDA {X}+ STA {X}+
TYA
110
XAY
DAA
111
XYX
NOP
iv
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B.3 Instruction Set
Arithmetic / Logic Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Mnemonic
ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm AND dp AND dp + X AND !abs AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS
Op Code
04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF
Byte No
2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1
Cycle No
2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 Arithmetic shift left
C
Operation
Flag
NVGBHIZC
Add with carry. A(A)+(M)+C
NV--H-ZC
Logical AND A (A)(M)
N-----Z-
76543210
"0"
N-----ZC
Compare accumulator contents with memory contents (A) -(M)
N-----ZC
Compare X contents with memory contents (X)-(M)
N-----ZC
Compare Y contents with memory contents (Y)-(M) 1'S Complement : ( dp ) ~( dp ) Decimal adjust for addition Decimal adjust for subtraction
N-----ZC
N-----ZN-----ZC N-----ZC
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No.
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Mnemonic
DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y DIV EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A ROL dp ROL dp + X ROL !abs
Op Code
A8 A9 B9 B8 AF BE 9B A4 A5 A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38
Byte No
1 2 2 3 1 1 1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3
Cycle No
2 4 5 5 2 2 12 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 Logical OR A (A)(M) Logical shift right Increment M (M)+1 Exclusive OR A (A)(M) Decrement M (M)-1
Operation
Flag
NVGBHIZC
N-----Z-
Divide : YA / X Q: A, R: Y
NV--H-Z-
N-----Z-
N-----ZC
N-----Z-
76543210 C "0"
N-----ZC
Multiply : YA Y x A
N-----Z-
N-----Z-
Rotate left through Carry
C 76543210
N-----ZC
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No.
76 77 78 79 80 81 82 83 84 85 86 87 88 89
Mnemonic
ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp XCN
Op Code
68 69 79 78 24 25 26 27 35 36 37 34 4C CE
Byte No
1 2 2 3 2 2 2 3 3 2 2 1 2 1
Cycle No
2 4 5 5 2 3 4 4 5 6 6 3 3 5
Operation
Rotate right through Carry
76543210 C
Flag
NVGBHIZC
N-----ZC
Subtract with Carry A ( A ) - ( M ) - ~( C )
NV--HZC
Test memory contents for negative or zero, ( dp ) - 00H Exchange nibbles within the accumulator A7~A4 A3~A0
N-----ZN-----Z-
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Register / Memory Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Mnemonic
LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + X LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA
Op Code
C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF
Byte No
2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1
Cycle No
2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 4 5 5 6 7 7 4 4 4 5 5 4 5 5 2 2 2 2 2 2 Load Y-register Y(M) Load X-register X (M) Load accumulator A(M)
Operation
Flag
NVGBHIZC
N-----Z-
X- register auto-increment : A ( M ) , X X + 1 Load memory with immediate data : ( M ) imm --------
N-----Z-
N-----Z-
Store accumulator contents in memory (M)A
--------
X- register auto-increment : ( M ) A, X X + 1 Store X-register contents in memory (M) X
--------
Store Y-register contents in memory (M) Y Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X sp Transfer X-register contents to accumulator: A X Transfer X-register contents to stack-pointer: sp X Transfer Y-register contents to accumulator: A Y
--------
N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z-
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39 40 41 42 43 44
XAX XAY XMA dp XMA dp+X XMA {X} XYX
EE DE BC AD BB FE
1 1 2 2 1 1
4 4 5 6 5 4
Exchange X-register contents with accumulator :X A Exchange Y-register contents with accumulator :Y A Exchange memory contents with accumulator (M)A Exchange X-register contents with Y-register : X Y
---------------
N-----Z-
--------
16-BIT operation
No.
1 2 3 4 5 6 7
Mnemonic
ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp
Op Code
1D 5D BD 9D 7D DD 3D
Byte No
2 2 2 2 2 2 2
Cycle No
5 4 6 6 5 5 5
Operation
16-Bits add without Carry YA ( YA ) ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (YA) - (dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits subtract without carry YA ( YA ) - ( dp +1) ( dp)
Flag
NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC
Bit Manipulation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Mnemonic
AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit
Op Code
8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B
Byte No
3 3 2 3 2 2 1 1 1 3 3 3 3 3
Cycle No
4 4 4 5 4 2 2 2 2 5 5 4 4 5
Operation
Bit AND C-flag : C ( C ) ( M .bit ) Bit AND C-flag and NOT : C ( C ) ~( M .bit ) Bit test A with memory : Z ( A ) ( M ) , N ( M 7 ) , V ( M6 ) Clear bit : ( M.bit ) "0" Clear A bit : ( A.bit ) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C ( C ) ( M .bit ) Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) Load C-flag : C ( M .bit ) Load C-flag with NOT : C ~( M .bit ) Bit complement : ( M .bit ) ~( M .bit )
Flag
NVGBHIZC -------C -------C MM----Z---------------------0 --0-----0--0---------C -------C -------C -------C --------
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15 16 17 18 19 20 21 22 23
OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs
6B 6B x1 0B A0 C0 EB 5C 3C
3 3 2 2 1 1 3 3 3
5 5 4 2 2 2 6 6 6
Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ~( M .bit ) Set bit : ( M.bit ) "1" Set A bit : ( A.bit ) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : ( M .bit ) C Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) Test and set bits with A : A-(M), (M) (M)(A)
-------C -------C ---------------------1 --1-----------N-----ZN-----Z-
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Branch / Jump Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mnemonic
BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL upage
Op Code
y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F
Byte No
2 3 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2
Cycle No
4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 Unconditional jump pc jump address
Operation
Branch if bit clear : if ( bit ) = 0 , then pc ( pc ) + rel Branch if bit set : if ( bit ) = 1 , then pc ( pc ) + rel Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel Branch if minus if ( N ) = 1 , then pc ( pc ) + rel Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel Branch if plus if ( N ) = 0 , then pc ( pc ) + rel Branch always pc ( pc ) + rel Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel Subroutine call M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, if !abs, pc abs ; if [dp], pcL ( dp ), pcH ( dp+1 ) . Compare and branch if not equal : if ( A ) ( M ) , then pc ( pc ) + rel. Decrement and branch if not equal : if ( M ) 0 , then pc ( pc ) + rel.
Flag
NVGBHIZC --------
-----------------------------------------------------------------------
--------
--------
--------
--------
U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H)
--------
24
TCALL n
nA
1
8
--------
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Control Operation & Etc.
No. Mnemonic Op Code Byte No Cycle No Operation
Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp 1, pcL ( 0FFDEH ) , pcH ( 0FFDFH) . Disable all interrupts : I "0" Enable all interrupt : I "1" No operation sp sp + 1, A M( sp ) sp sp + 1, X M( sp ) sp sp + 1, Y M( sp ) sp sp + 1, PSW M( sp ) M( sp ) A , sp sp - 1 M( sp ) X , sp sp - 1 M( sp ) Y , sp sp - 1 M( sp ) PSW , sp sp - 1 Return from subroutine sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pcL M( sp ), sp sp + 1, pcH M( sp ) Stop mode ( halt CPU, stop oscillator ) --------------restored --------
Flag
NVGBHIZC
1
BRK
0F
1
8
---1-0--
2 3 4 5 6 7 8 9 10 11 12 13
DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET
60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F
1 1 1 1 1 1 1 1 1 1 1 1
3 3 2 4 4 4 4 4 4 4 4 5
-----0------1---------
14 15
RETI STOP
7F EF
1 1
6 3
restored --------
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C. SOFTWARE EXAMPLE
;***************************************************************************** ; Title: GMS81C7216/7016 (GMS800 Series) Demonstration Program * ; Company: MagnaChip Semiconductor Ltd. ; Contents: LCD DISPLAY & DUAL THERMOMETER * ;***************************************************************************** ; ;******** DEFINE I/O PORT & FUNCTION REGISTER ADDRESS ********* ; R0 EQU 0C0H ;port R0 register R1 EQU 0C1H ;port R1 register R2 EQU 0C2H ;port R2 register R3 EQU 0C3H ;port R3 register R4 EQU 0C4H ;port R4 register R5 EQU 0C5H ;port R5 register ; R0DD EQU 0C8H ;port R0 data I/O direction register R1DD EQU 0C9H ;port R1 data I/O direction register R2DD EQU 0CAH ;port R2 data I/O direction register R3DD EQU 0CBH ;port R3 data I/O direction register R4DD EQU 0CCH ;port R4 data I/O direction register R5DD EQU 0CDH ;port R5 data I/O direction register ; R0PU EQU 0D0H ;port R0 Pull-up selection register R1PU EQU 0D1H ;port R1 Pull-up selection register R2PU EQU 0D2H ;port R2 Pull-up selection register R3PU EQU 0D3H ;port R3 Pull-up selection register ; R0CR EQU 0D4H ;port R0 Type selection register R1CR EQU 0D5H ;port R1 Type selection register R2CR EQU 0D6H ;port R2 Type selection register R3CR EQU 0D7H ;port R3 Type selection register ; IEDS EQU 0D8H ;External interrupt edge selection register PMR EQU 0D9H ;Alternative port mode register IENL EQU 0DAH ;int. enable register low IENH EQU 0DBH ;int. enable register high IRQL EQU 0DCH ;int. request flag register low IRQH EQU 0DDH ;int. request flag register high SLPR WDTR TM0 TDR0 TM1 TDR1 T1PPR T1PDR PWM0HR TM2 TDR2 TM3 TDR3 T3PPR T3PDR PWM1HR ADCM ADR WTMR KSMR LCDM LCDPM RPR BITR CKCTLR SCMR PFDR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0DEH 0DFH 0E0H 0E1H 0E2H 0E3H 0E3H 0E4H 0E5H 0E6H 0E7H 0E8H 0E9H 0E9H 0EAH 0EBH 0ECH 0EDH 0EFH 0F0H 0F1H 0F2H 0F3H 0F4H 0F4H 0F5H 0FBH ;sleep mode register ;Watchdog timer register ;Timer 0 mode register ;Timer 0 data register ;Timer 1 mode register ;Timer 1 data register ;PWM0 period register ;Timer 1 pulse duty register ;PWM0 high register ;Timer 2 mode register ;Timer 2 data register ;Timer 3 mode register ;Timer 3 data register ;PWM1 period register ;Timer 3 pulse duty register ;PWM1 high register ;ADC mode register ;ADC result data register ;Watch timer mode register ;Key scan mode register ;LCD mode register ;LCD port mode register ;RAM paging register ;Basic interval timer data register ;Clock control register ;System clock mode register ;Power fail detector ;buzzer data register ;Serial mode register ;Serial data buffer register ************ ;Save Registers to Stacks *
BUR EQU 0FDH SMR EQU 0FEH SIOD EQU 0FFH ; ;*********** MACRO DEFINITION ; R_SAVEMACRO
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PUSH
X PUSH ENDM ; R_RSTRMACRO ;Restore Register from Stacks POP Y POP X POP A ENDM ; ;*********** CONSTANT DEFINITION *********** ; ; ; ;************************************************************************** ; RAM ALLOCATION * ;************************************************************************** TEMP0 DS 1 TEMP1 DS 1 TEMP2 DS 1 FLAG1 DS 1 RPTEN KEYONF ACTKEY TOGMO3 DUAL_T OUTSIDE FLAG2 F200MS F20MS F_1MIN LPM RPM STATUS RPTKEY F_CLOCK F_ON DISPSIGN DISPRAM DISPRAM1 ONDO LHOUR LMINUTE RHOUR RMINUTE TIMESET TSFLAG TSLPM TSRPM BLINKCNT ; NEWKY OLDKY PORTDT KEYNM KEYDT TOTLKY CHATFL R0BUF DGTCNT MODE SUBMODE BSCTIME TEMPCNT HZCNT EQU EQU EQU EQU EQU EQU DS EQU EQU EQU EQU EQU DS EQU EQU EQU DS DS DS DS DS DS DS DS DS DS EQU EQU DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS 1,FLAG1 2,FLAG1 3,FLAG1 4,FLAG1 5,FLAG1 6,FLAG1 1 0,FLAG2 1,FLAG2 2,FLAG2 3,FLAG2 4,FLAG2 1 7,STATUS 6,STATUS 0,STATUS 1 1 4 2 1 1 1 1 4 1 0,TSFLAG 1,TSFLAG 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ;TEMP. ;LEFT TIME, RIGHT TIME ;LEFT WATCH COUNT ;RIGHT WATCH COUNT BUF. ;WATCH SET BUFFER ;TIME SET LEFT PM ;TIME SET RIGHT PM ;BLINK COUNTER 0~250 LOOP ;SET RPTEN(REPEAT KEY ENABLE) AFTER 1 SEC. ;KEYSCAN ;AT ONCE, KEY VALID ;MODE 3 (PORT TOGGLE) ;INSIDE & OUTSIDE TEMP. DUAL DISPLAY ;INSIDE TEMP or OUTSIDE TEMP.
A PUSH Y
;WTIMER ;LEFT TIME PM FLAG ;RIGHT TIME PM FLAG
PWMF DS 1 PERIOD EQU 0,PWMF ; ;************************************************************************** ; INTERRUPT VECTOR TABLE * ;**************************************************************************
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;
; ;************************************************************************** ; MAIN PROGRAM * ;************************************************************************** ; ORG 0C000H ;Program Start Address ;ORG 0E000H ; 8K ROM VERSION ; RESET: LDM WDTR,#0 LDM RPR,#1 ; CLRG LDX #0 RAMCLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ ;M(X) <- A, then X <- X+1 CMPX #0C0H ;X = #0C0H ? BNE RAMCLR SETG LDX #0 RAMCLR1: LDA #0 ;RAM Clear(!0100H->!011AH) STA {X}+ ;M(X) <- A, then X <- X+1 CMPX #1BH ;X = #01BH ? BNE RAMCLR1 CLRG ; LDX #0FFH ;Stack Pointer Initial TXSP ;SP. <- #0FFH ; ;******** USER RAM INITIALIZE ********** ; ; LDM MODE,#4 ; LDM SUBMODE,#1 SET1 LPM ;KST PM 12:00 JUST NOON LDM LHOUR,#12H LDM LMINUTE,#00H LDM RHOUR,#03H ;UTC AM 03:00 LDM RMINUTE,#00H SET1 OUTSIDE SET1 F_ON ;POWER ON ; ;********** PORT INITIALIZE ************ ; LDM LCDPM,#0 ;SEG0~SEG23 are used LDM R0,#0 ;I/O Port Data Clea LDM R1,#0 ;I/O Port Data Clear LDM R2,#0 LDM R3,#0 LDM R0DD,#1111_0001B ;R05,R06,R07: output for Keyscan LDM R1DD,#0000_0000B LDM R2DD,#0000_0000B ;R20~R23: input for keyscan LDM R3DD,#0000_0100B LDM R2PU,#0000_1111B ;R20~R23 pull-up active ; ;***** CONTROL REGISTER INITIALIZE ***** ; LDM CKCTLR,#0 ;WAKE UP TIME = 0.0625 sec ;(1/32768)*8*256 = 0.0625sec LDM TDR0,#249 ;8us x (249+1) = 2ms LDM TM0,#0000_1111B ;8BIT Timer,8us,Start Count-up LDM TDR1,#249 ;2us x (249+1) = 500us LDM TM1,#0000_1111B ;Timer1(8bit),32us,Start Count-up LDM TM3,#1010_1011B
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW
0FFE0H NOT_USED ; Timer-3 NOT_USED ; Timer-2 WTIMER ; Watch Timer INT_AD ; A/D CON. NOT_USED ; Serial I/O NOT_USED ; Not used NOT_USED ; Not used NOT_USED ; Int.2 TIMER1 ; Timer-1 TIMER0 ; Timer-0 INT1 ; Int.1 INT0 ; Int.0 NOT_USED; Watch Dog Timer NOT_USED; BIT INT_KEY ; Key Scan(Only GMS81C7008/7016) RESET ; Reset
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LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM LDM EI ; BBC CALL CLR1
T3PPR,#99 T3PDR,#50 PWM1HR,#00H PMR,#80H IRQH,#0 IRQL,#0 IENL,#1111_1111B IENH,#1111_1111B IEDS,#0001_0101B KSMR,#0000_0001B WTMR,#48H LCDM,#70H SCMR,#0 ;Clear All Interrupts Requeat Flags ;INT2,ADC,WT,T2,T3 ;BIT,WDT,INT0,INT1,T0,T1 ;External Int. Falling edge select ;R10 KEY INTERRUPT ;ENABLE WT COUNTER, 2Hz, SELECT SUBCLOCK ;CLK=fsub/64, 1/4duty, internal Bias ;1/2, MAIN OSC. ;Enable Interrupts KEYONF,EXE1 KEYDECODE KEYONF ;TEST IF KEY IS PRESSED ;CLEAR KEY FLAG
LOOP: EXE1:
BBC F20MS,NEXT1 CLR1 F20MS ; ;*****EVERY 20MS***** ; CALL MODEEXE CALL MODE1EXE CALL MODE3EXE CALL LCDDGT CALL LCDDOT CALL ADCEXE CALL LKEYSCAN BBC F200MS,ELOOP CLR1 F200MS ; ;*****EVERY 200MS***** ; CALL WIND
;SETTING DISPLAY MEMORY ;DURING CLOCK, ;7-Segments Display ;Dot Display ;ADC execution
NEXT1:
ELOOP:
EXE2:
BBS F_ON,EXE2 CLR1 R0.7 CLR1 R0.6 CLR1 R0.5 CLR1 R0.4 STOP NOP NOP IF [F_1MIN] CLR1 F_1MIN CALL MODEEXE CALL LCDDGT CALL LCDDOT ENDIF CALL LKEYSCAN
;FOR ;FOR ;FOR ;FOR
WAKE-UP WAKE-UP WAKE-UP WAKE-UP
BY BY BY BY
NEXT NEXT NEXT NEXT
KEY KEY KEY KEY
;7-Segments Display ;Dot Display
JMP LOOP ; ;************************************************************************** ; TIMER0,INTERRUPT ROUTINE(2ms) * ;************************************************************************** ; TIMER0: R_SAVE ;Save Registers to Stacks CLRG CALL MAKE10MS ;SET every 10ms R_RSTR ;Restore Registers from Stacks RETI ; ;************************************************************************** ; TIMER1 * ;************************************************************************** ; TIMER1: R_SAVE CLRG R_RSTR
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RETI ; ;************************************************************************** ; WATCH TIMER 4Hz * ;************************************************************************** ; WTIMER: R_SAVE CLRG NOT1 R0.0 INC LDA CMP BNE LDM SET1 CALL WT5: R_RSTR RETI HZCNT HZCNT #120 WT5 HZCNT,#0 F_1MIN INC1MIN
; ;************************************************************************** ; PORT INTERRUPT * ;************************************************************************** ; INT_KEY: R_SAVE CLRG BBS CHATFL.7,IK8 BBS F_ON,IK8 LDX #3 LDM KSMR,#0 ;MAKE R10 TO BE NORMAL INPUT WW: WW2: WW3: LDY LDA DEC BNE DEC BNE LDA ROR BCS DEC BNE LDM SET1 SET1 LDM LDM R_RSTR RETI #2 #8 A WW3 Y WW2 R1 A IK8 X WW SCMR,#0 F_ON CHATFL.7 OLDKY,#0CH KSMR,#1 ;24ms wait
;READ R10
;MAIN OSC.
IK8:
; ;************************************************************************** ; EXTERNAL INTERRUPT 0 * ;************************************************************************** ; INT0: R_SAVE CLRG R_RSTR RETI ; ;************************************************************************** ; EXTERNAL INTERRUPT 1 * ;************************************************************************** ; INT1: CLRG RETI ; ;************************************************************************** ; ADC INTERRUPT * ;************************************************************************** ; INT_AD: RETI ; ;***********************************************************************
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; Subject: LCDDGT ; LCD 7-SEG. DIGIT DISPLAY (TMEP,LTIME,RTIME * ;*********************************************************************** ; Entry: DGTCNT (DIGIT COUNTER) * ; X (START ADDRESS) * ; Output: Output SEG_PORT (SEG0~SEG23) * ; Output COM_PORT (COM0~COM3) * ;*********************************************************************** ; EXAMPLE) __ __ __ __ * ; DGTCNT=9 | || | | || | * ; X=LMINUTE |---| |---| |---| |---| * ; |___| |___| |___| |___| * ; LMINUTE+1 LMINUTE * ;*********************************************************************** ; LCDDGT: LDM DGTCNT,#9 LDX #DISPRAM GOLCD: LDA {X} PUSH X if [DGTCNT.0] ;WHEN DIGIT IS EVEN NUMBER, AND #0F0H ;WHEN DIGIT IS ODD NUMBER, XCN CALL LCDDSP ;HIGHER 4 NIBBLE IS DISPLAYED POP X else AND #0FH ;LOWER 4 NIBBLE IS DISPLAYED CALL LCDDSP POP X INC X endif DEC DGTCNT BPL GOLCD RET ; ;********* ONE DIGIT DISPLAY ********** ; LCDDSP: TAY ; ;****** ZERO SURPRESS TO BLANK ****** ; BNE GOCONT ;IF A=0 THEN SURPRESS LDA DGTCNT CMP #9 BEQ BLNK CMP #7 BEQ BLNK CMP #3 BEQ BLNK BRA GOCONT BLNK: LDY #0AH ; GOCONT: LDA !FONT+Y ;LOAD FONT DATA STA TEMP0 ;STORE 7-SEG FONT LDM TEMP2,#7 ;SHIFT COUNTER INITIALIZE LDY DGTCNT ;GET OFFSET LCD ADDRESS FOR DGTCNT LDA #14 MUL TAY DPL1: LDA !FONTD0+Y ;GET LCD RAM ADDRESS TAX ;STORE LCD RAM ADDRESS INC Y ;INCREMENT POINTER LDA !FONTD0+Y ;GET BIT POSITION STA TEMP1 ;STORE BIT POSITION ROR TEMP0 BCS DPL3 LDA #0FFH ;CLEAR BIT DISPLAY RAM ROL A DEC TEMP1 BPL $-3 SETG AND {X} BRA DPL5 DPL3: LDA #00H ;SET BIT DISPLAY RAM ROL A DEC TEMP1 BPL $-3 SETG OR {X} DPL5: STA {X}
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CLRG INC DBNE RET
Y TEMP2,DPL1
FONTD0 DB 13H,1H,13H,2H,13H,0H,13H,3H,0CH,3H,0CH,2H,0CH,0H ;RMINUTE0 FONTD1 DB 12H,1H,12H,2H,12H,0H,12H,3H,05H,3H,05H,2H,05H,0H ;RMINUTE1 FONTD2 DB 06H,1H,06H,2H,06H,0H,06H,3H,01H,3H,01H,2H,01H,0H ;RHOUR0 FONTD3 DB 80H,0H,01H,1H,01H,1H,80H,0H,80H,0H,80H,0H,80H,0H ;RHOUR1 FONTD4 DB 02H,1H,02H,2H,02H,0H,02H,3H,15H,3H,15H,2H,15H,0H ;LMINUTE0 FONTD5 DB 09H,1H,15H,1H,09H,0H,09H,3H,16H,0H,16H,1H,09H,2H ;LMINUTE1 FONTD6 DB 14H,1H,14H,2H,14H,0H,14H,3H,00H,3H,00H,2H,00H,0H ;LHOUR0 FONTD7 DB 80H,0H,08H,2H,08H,2H,80H,0H,80H,0H,80H,0H,80H,0H ;LHOUR1 FONTD8 DB 0BH,2H,0BH,0H,0BH,3H,0BH,1H,17H,1H,17H,0H,17H,3H ;ONDO0 FONTD9 DB 0FH,2H,0FH,0H,0FH,3H,0FH,1H,10H,1H,10H,0H,10H,3H ;ONDO1 ; ;************************************************************************** ; 7-SEGMENT PATTERN DATA * ; _a_ * ; f | g |b * ; |---| * ; e |___|c * ; d .h * ;************************************************************************** ; FONT Segment: DB DB DB DB DB DB DB DB DB DB DB DB EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU SETC STC STC STC STC LDCB STC LDCB STC LDC STC LDCB STC IF ldc stc ldcb stc ELSE LDCB STC 2,116H 2,10EH 2,107H 0,111H 1,10EH 0,10EH 1,108H 3,108H 1,104H 0,107H 2,10AH 3,10AH 3,104H _LCOLON _S1 _ONDO _C F_ON _SAVE DUAL_T _RCOLON LPM _LPM LPM _LAM [DUAL_T]==0 RPM _RPM RPM _RAM DUAL_T _RPM ;AM,PM SETTING hgfe dcba 0011_1111B 0000_0110B 0101_1011B 0100_1111B 0110_0110B 0110_1101B 0111_1101B 0000_0111B 0111_1111B 0110_1111B 0000_0000B 0100_0000B ; ; ; ; ; ; ; ; ; ; ; ; To be displayed Digit Number 0 1 2 3 4 5 6 7 8 9 A B "0"
"8" "9" "BLANK" "BAR"
_LCOLON _RCOLON _ONDO _C _RAM _RPM _LAM _LPM _OUTSIDE _INSIDE _S1 _SNOW _SAVE ; LCDDOT:
;TURN OFF THE AM, PM
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STC ENDIF LDC STC LDCB STC
_RAM OUTSIDE _OUTSIDE OUTSIDE _INSIDE
RET ; ;*********************************************** ; Subject: ANY EXECUTION * ;*********************************************** ; DESCRIPTION: EVERY 20MS * ; * ;*********************************************** ; MODEEXE: IF [OUTSIDE] LDX #0 ELSE LDX #1 ENDIF LDA STA LDA STA IF IF ONDO+X DISPRAM SIGN+X DISPSIGN ;COPY ONDO DATA TO DISPRAM
[DISPSIGN.0] [DISPRAM] < #10 LDA #0B0H OR DISPRAM STA DISPRAM CLRC STC _SNOW ELSE SETC STC _SNOW ENDIF ELSE CLRC STC _SNOW ENDIF MX1: LDX LDA STA DEC BPL BBC LDA STA IF LDX ELSE LDX ENDIF LDA STA LDA ROR IF IF C #3 LHOUR+X DISPRAM1+X X MX1 DUAL_T,MX2 #0AAH DISPRAM1+2 [OUTSIDE] #1 #0 ONDO+X DISPRAM1+3 SIGN+X A
;IF MINUS ONDO, THEN "-" DISPLAY
;MOVE TIME_BUF. TO DISP_BUF.
;IF SINGLE TEMP. MODE, SKIP ;MAKE ERASE DISP BUF. WITCH ;WILL BE DISPLAYED TEMP. ;IF DUAL TEMP. MODE ;IF MAIN=OUSIDE, THEN SELECT INSIDE ;IF MAIN=INSIDE, THEN SELECT OUTSIDE
;GET BIT0 OF SIGN ;COPY SIGN TO CARRY ;IF MINUS ONDO, THEN "-" DISPLAY ;EXE) BB-4
[DISPRAM1+3] < #10 LDA #0B0H OR DISPRAM1+3 STA DISPRAM1+3 ELSE LDM DISPRAM1+2,#0ABH ENDIF ELSE IF [DISPRAM1+3] < #10 LDA #0A0H OR DISPRAM1+3 STA DISPRAM1+3 ENDIF
;EXE) B-14
;EXE) BB-4
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ENDIF MX2: RET
; ;*********************************************** ; Subject: MODE 1 EXECUTION * ;*********************************************** ; DESCRIPTION: CLOCK SET * ; * ;*********************************************** ; MODE1EXE: LDA MODE AND #0F0H CMP #10H ;IF MODE=1x BNE MB3 LDX #3 MB1: LDA TIMESET+X ;TIMESET BUF. COPIED TO DISP BUF. STA DISPRAM1+X ;4BYTE & 2 BIT DEC X BPL MB1 LDC TSLPM STC LPM LDC TSRPM STC RPM ; LDA MODE CMP #10H ;TEST IF LEFT TIME SET MODE ? BEQ MO10 CMP #11H BEQ MO11 ;TEST IF RIGHT TIME SET MODE ? BRA MB3 MO10: LDA CMP BCS LDA STA STA RET LDA CMP BCS LDA STA STA BRA BLINKCNT #125 MB3 #0AAH DISPRAM1 DISPRAM1+1 BLINKCNT #125 MB3 #0AAH DISPRAM1+2 DISPRAM1+3 MB3 ;IF LESS THAN 124, OFF
MB3: MO11:
;IF LESS THAN 124, OFF
; ;*********************************************** ; Subject: MODE 3 EXECUTION * ;*********************************************** ; DESCRIPTION: All pin goes low and high * ; repeatly every 20ms, rectangle wave output * ; * ;*********************************************** ; MODE3EXE: LDA MODE CMP #3 BNE MO2 LDA SUBMODE DEC A ;BECAUSE INITIAL NO.=1 ROL A ;EIGHT TIMES ROL A ROL A NOT1 TOGMO3 BBC TOGMO3,MO1 CLRC ADC #4 ;ADD OFFSET MO1: TAY LDA !PPORT+Y AND #0001_1111B OR R0BUF STA R0BUF STA R0 LDA !PPORT+1+Y STA R1 LDA !PPORT+2+Y STA R2
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MO2: PPORT
LDA STA RET DB DB DB DB DB DB DB DB DB DB DB DB DB DB
!PPORT+3+Y R3 00H,00H,00H,00H 00H,00H,00H,00H 0FFH,0FFH,0FFH,0FFH 0FFH,0FFH,0FFH,0FFH 00H,00H,00H,00H 0FFH,0FFH,0FFH,0FFH 00H,00H,00H,00H 0FFH,00H,0FFH,00H 00H,0FFH,00H,0FFH 00H,00H,00H,00H 00H,0FFH,00H,0FFH 0FFH,00H,0FFH,00H 55H,55H,55H,55H 0AAH,0AAH,0AAH,0AAH
; ;*********************************************** ; Subject: Set falg at every 20ms * ;*********************************************** ; MAKE10MS: SETC LDA #0 ADC BSCTIME DAA STA BSCTIME BNE $+4 SET1 F200MS ;SET F200MS EVERY 200ms AND #0FH BNE $+4 SET1 F20MS ;SET F20MS EVERY 20ms ; INC BLINKCNT ;USED IN MODE0(CLOCK SET) LDA BLINKCNT CMP #250 BNE MZ1 LDM BLINKCNT,#0 MZ1: RET ; ;*********************************************** ; Subject: Analog to Digital Conversion * ;*********************************************** ; It is called in main routine every 20ms ADCNT DS 2 ADR_AVR DS 2 ADTTL DS 4 ADFLAG DS 1 AD_CH EQU 0,ADFLAG SIGN DS 2 DIVISOR EQU 250 ; ; :-------: :-------: ; :ADR_AVR: :ADR_AVR: ; : :: : ; :OUTSIDE: :INSIDE : ; :CH4 : :CH5 : ; :-------: :-------: ; ADCEXE: IF [AD_CH]== 0 LDM ADCM,#52H ;AD START CH4 LDX #0 ;SET TO 0 INDEX POINTER ELSE LDM ADCM,#56H ;AD START CH5 LDX #1 ;SET TO 1 INDEX POINTER ENDIF ADWAIT: LDY DEC BBS CMPY BNE #20 Y ADCM.0,GOGET #0 ADWAIT ;WAIT ADC END
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GOGET:
CLRC LDA ADR ADC ADTTL+X STA ADTTL+X LDA #0 ADC ADTTL+2+X STA ADTTL+2+X ; INC ADCNT+X LDA ADCNT+X IF A == #DIVISOR LDA #0 STA ADCNT+X LDY ADTTL+2+X LDA ADTTL+X PUSH X LDX #DIVISOR DIV POP X STA ADR_AVR+X LDA #0 STA ADTTL+X STA ADTTL+2+X LDA IF LDA ENDIF IF LDA ENDIF CMP ROL SETC SBC TAY LDA STA ENDIF ADR_AVR+X A < #65 #65 A > #240 #240 #181 SIGN+X #65 !ADTABLE1+Y ONDO+X AD_CH
;UP8 LO8 ;ADTTL2|ADTTL0 = CH4 DATA ;ADTTL3|ADTTL1 = CH5 DATA
;GET AVERAGE VALUE
;DIVIDE BY DIVISOR
;CLEAR SUM BUF.
;IGNORE BELOW 65 ;MAX. 240 ;MAKE SIGN ;COPY TO MINUS OR PLUS
ADCQUIT: ; ; ADTABLE
NOT1 RET DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
ADTABLE1
50H,49H,49H,48H,48H,47H 47H,46H,46H,45H,45H,44H,44H,43H,43H,42H 41H,41H,40H,40H,40H,39H,39H,38H,38H,37H 37H,36H,36H,35H,35H,34H,34H,33H,33H,32H 32H,31H,31H,30H,30H,30H,29H,29H,28H,28H 27H,27H,26H,26H,25H,25H,24H,24H,24H,23H 23H,22H,22H,22H,21H,21H,20H,20H,20H,20H 19H,19H,18H,18H,17H,17H,16H,16H,15H,15H 15H,14H,14H,14H,13H,13H,13H,12H,12H,12H 11H,11H,11H,10H,10H,10H,09H,09H,09H,08H 08H,07H,07H,07H,06H,05H,05H,04H,04H,04H 03H,03H,02H,02H,01H,01H,00H,00H,00H,01H 01H,02H,02H,03H,03H,04H,04H,05H,05H,06H 06H,07H,07H,08H,08H,09H,09H,10H,10H,11H 11H,12H,12H,13H,13H,14H,15H,15H,16H,17H 17H,18H,18H,19H,19H,20H,20H,21H,21H,22H 23H,23H,24H,24H,25H,25H,26H,27H,28H,29H 30H,31H,32H,33H,34H,35H,36H,37H,38H,39H 40H,41H,42H 50H,50H,50H,49H,49H,48H 48H,47H,47H,46H,46H,45H,45H,44H,44H,43H 43H,42H,41H,40H,39H,38H,37H,36H,35H,34H 35H,35H,34H,34H,33H,33H,32H,32H,31H,31H 30H,30H,29H,29H,28H,28H,27H,27H,26H,26H 26H,25H,25H,25H,24H,24H,24H,23H,23H,23H 22H,22H,22H,21H,21H,21H,20H,20H,20H,20H 19H,18H,18H,18H,17H,17H,17H,16H,16H,16H 15H,15H,15H,14H,14H,14H,13H,13H,13H,12H 12H,11H,11H,10H,10H,09H,09H,09H,08H,08H 07H,07H,06H,06H,05H,05H,04H,04H,04H,03H 03H,03H,02H,02H,02H,01H,01H,01H,00H,00H 01H,01h,02H,02H,03H,03H,04H,04H,05H,05H 06H,06H,07H,07H,08H,08H,09H,09H,10H,10H 11H,11H,12H,12H,13H,13H,14H,15H,15H,16H 16H,16H,17H,18H,18H,19H,19H,20H,20H,21H
; 65~ 70 ; 71~ 80 ; 81~ 90 ; 91~100 ;101~110 ;111~120 ;121~130 ;131~140 ;141~150 ;151~160 ;161~170 ;171~180 ;181~190 ;191~200 ;201~210 ;211~220 ;221~230 ;231~240 ; 65~ 70 ; 71~ 80 ; 81~ 90 ; 91~100 ;101~110 ;111~120 ;121~130 ;131~140 ;141~150 ;151~160 ;161~170 ;171~180 ;181~190 ;191~200 ;201~210 ;211~220
65->+50'C 83->+40'C 105->+30'C 129->+20'C 154->+10'C 178-> 0'C
199->-10'C 217->-20'C 231->-30'C 65->+50'C 83->+40'C 105->+30'C 129->+20'C 154->+10'C 178-> 0'C
199->-10'C 217->-20'C
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; ;*********************************************** ; Subject: KEYDECODE * ;*********************************************** ; * ;*********************************************** ; REPEAT EQU #1000_0000B CLOCK EQU #0100_0000B PWRON EQU #0000_0001B KEYDECODE: LDA LDY MUL TAY LDA STA LDA STA LDA STA CALL BCC JMP ; KEY: DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB DW DB QUIT: NOKEY: RET CONDICHK: LDA OR SBC BEQ BCS SETC RET CLRC RET KEYDT #3 !KEY+Y TEMP0 !KEY+1+Y TEMP1 !KEY+2+Y TEMP2 CONDICHK QUIT [TEMP0] NOKEY 0 NOKEY 0 NOKEY 0 NOKEY 0 NOKEY 0 NOKEY 0 NOKEY 0 DOWNKEY PWRON+REPEAT NOKEY 0 DUALKEY PWRON SWAPKEY PWRON NOKEY 0 POWERKEY PWRON CLOCKKEY PWRON+CLOCK HOURKEY PWRON+REPEAT+CLOCK MINUTEKEY PWRON+REPEAT+CLOCK NOKEY 0 UPKEY PWRON+REPEAT NOKEY 0 ;0 ;1 ;2 ;3 ;4 ;5 ;6 ;7 ;8 ;9 ;A ;B ;C ;D ;E ;F ;10 ;11 ;12
DB DB DB
21H,22H,23H,23H,24H,24H,25H,25H,26H,27H ;221~230 28H,29H,30H,31H,32H,33H,34H,35H,36H,37H ;231~240 231->-30'C 38H,39H,40H
CDC9: CDC10: ;
TEMP2 STATUS TEMP2 CDC9 CDC10
;PASS ;SKIP
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;*********************************************************** ; DISPLAY SWAP KEY (TEMP. DISPLAY SWAP) * ;*********************************************************** ; SWAPKEY: NOT1 OUTSIDE RET ; ;*********************************************************** ; DUAL KEY * ;*********************************************************** ; DUALKEY: NOT1 DUAL_T RET ; ;*********************************************************** ; POWER KEY * ;*********************************************************** ; POWERKEY: CLR1 F_ON IF [F_ON] ELSE LDM SCMR,#2 CLR1 DUAL_T LDM MODE,#0 SET1 F20MS ENDIF RET ; ;*********************************************************** ; CLOCK KEY * ;*********************************************************** ; CLOCKKEY: SET1 F_CLOCK LDM BLINKCNT,#0 LDA MODE ; 10->11 CMP #10H ; 11->00 BNE CL1 ; ETC. -> 10 LDM MODE,#11H BRA QUIT CL1: CMP #11H BNE CL2 LDM MODE,#0 CLR1 F_CLOCK CALL SETTO_CNT LDC TSLPM STC LPM LDC TSRPM STC RPM LDM HZCNT,#0 CLR1 F_1MIN BRA CLQ CL2: LDM CLR1 CALL LDC STC LDC STC RET MODE,#10H DUAL_T CNTTO_SET LPM TSLPM RPM TSRPM
CLQ: ; SETTO_CNT: LDX #3 CL11: LDA TIMESET+X STA LHOUR+X DEC X BPL CL11 RET ; CNTTO_SET: LDX #3 CL3: LDA LHOUR+X STA TIMESET+X DEC X BPL CL3 RET ; ;*********************************************************** ; HOUR/MINUTE KEY * ;*********************************************************** ; HOURKEY: LDA MODE
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HO1: HO2:
AND #0F0H CMP #10H BNE HO1 LDM BLINKCNT,#125 LDA MODE CMP #10H BNE HO2 SETC LDA #0 ADC TIMESET DAA IF A==#12H NOT1 TSLPM ENDIF IF A==#13H LDA #1 ENDIF STA TIMESET RET CMP #11H BNE HO1 SETC LDA #0 ADC TIMESET+2 DAA IF A==#12H NOT1 TSRPM ENDIF IF A==#13H LDA #1 ENDIF STA TIMESET+2 BRA HO1 MODE #0F0H #10H MT3 BLINKCNT,#125 #3 MODE #10H MT1 #1 #0 TIMESET+X #60H MT2 #0 TIMESET+X
;IF MODE=10H, THEN LEFT TIME SET ;INC. LEFT HOUR 1UP
;ADJUST AM,PM FLAG
;INC. RIGHT HOUR 1UP
;ADJUST AM,PM FLAG
MINUTEKEY: LDA AND CMP BNE LDM LDX LDA CMP BNE LDX SETC LDA ADC DAA CMP BNE LDA STA RET
MT1:
MT2: MT3: ; ;*********************************************** ; UP /DOWN KEY * ;*********************************************** ; UPKEY: BBS PERIOD,PRU LDA PWM1HR AND #0000_0011B CMP #3 BNE UPK1 LDA T3PDR CMP #0FFH BNE UPK1 UPK0: RET UPK1: INC BNE INC BRA T3PDR UPK0 PWM1HR UPK0
PRU: DOWNKEY:
BBS LDA AND CMP
PERIOD,PRD PWM1HR #0000_0011B #0
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DNK1:
DNK2: PRD:
BNE LDA CMP BEQ DEC LDA CMP BNE DEC RET
DNK1 T3PDR #0 UPK0 T3PDR T3PDR #0FFH DNK2 PWM1HR
PWMMODE: ; ;*********************************************************** ; PLUS KEY * ; * ; When MODE=3, PRESS PULS KEY, SUBMODE IS INCRESED * ; When MODE=3, PRESS MINUS KEY, SUBMODE IS DECRESED * ; * ;*********************************************************** ; ; ;*********************************************** ; Subject: KEYSCAN * ;*********************************************** ; STROBE OUT: R05,R06,R07 * ; READ PORT : R20,R21,R22,R23 * ; * ;*********************************************** ; LKEYSCAN: BBS KEYONF,KS7 LDM KEYNM,#1 LDM TOTLKY,#0 LDM NEWKY,#0 LDY #3 ;INITIALIZE STROBE LINE KS1: CMPY #3 BNE $+4 CLR1 R0.4 ;OUTPUT STROBE SIGNAL CMPY #2 BNE $+4 CLR1 R0.5 ;OUTPUT STROBE SIGNAL CMPY #1 BNE $+4 CLR1 R0.6 ;OUTPUT STROBE SIGNAL CMPY #0 BNE $+4 CLR1 R0.7 ;OUTPUT STROBE SIGNAL ; NOP NOP LDA R2 STA PORTDT ;READ KEY IN PORT AND #0FH CMP #0FH ;IF KEY IS PRESSED ? BNE KS2 CLRC ;KEYNM + 4 -> KEYNM LDA #4 ADC KEYNM STA KEYNM BRA KS5 ; KS2: LDX #3 ;INITIALIZE SHIFT COUNTER KS3: ROR PORTDT BCS KS4 INC TOTLKY ;IF TOTLKY IS ABOVE 2, THEN QUIT LDA TOTLKY CMP #20 BEQ KS7 LDA KEYNM ;KEYNM -> NEWKY STA NEWKY KS4: INC KEYNM DEC X BPL KS3 KS5: SET1 R0.4 SET1 R0.5
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KS6:
KS7: KS8:
KS81: KS9: KS10:
SET1 SET1 DEC BPL LDA CMP BNE LDA STA LDM CLR1 CLR1 CLR1 RET LDA CMP BNE BBS LDA AND CMP BCC LDA STA SET1 LDM SET1 BRA INC BRA LDA AND BBS CMP BCC SET1 BRA CMP BCC BBC SET1 BRA
R0.6 R0.7 Y KS1 NEWKY #0 KS8 NEWKY OLDKY CHATFL,#0 RPTKEY ACTKEY RPTEN NEWKY OLDKY KS6 CHATFL.7,KS10 CHATFL #0111_1111B #5 KS9 NEWKY KEYDT ACTKEY CHATFL,#80H KEYONF KS7 CHATFL KS7 CHATFL #0111_1111B RPTEN,KS11 #25 KS9 RPTEN KS81 #3 KS9 ACTKEY,KS7 RPTKEY KS81
;TEST NEXT LINE ;WHEN NO KEY IS PRESSED, ;INITIALIZE NEWKY,OLDKY,CHATFL
;SET1 CHATFL.7 & SET TO 0
;REPEAT KEY
KS11:
; ;*********************************************** ; Subject: Increase 1 minute * ;*********************************************** ; INC1MIN: LDX #LMINUTE CALL MIN1UP LDX #RMINUTE CALL MIN1UP RET ; MIN1UP: SETC LDA #0 ; LMINUTE <- LMINUTE + 1 ADC {X} DAA IF A ==#60H SETC LDA #0 ENDIF STA {X} BCC INC1 DEC X LDA #0 ADC {X} DAA IF A==#12H IF X==#LHOUR NOT1 LPM ELSE NOT1 RPM ENDIF ENDIF IF A==#13H LDA #1 ENDIF STA {X} INC1: RET
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; ;*********************************************** ; Subject: WIND DISPLAY * ;*********************************************** ; WIND: LDA TEMPCNT CLRC STC 10DH.0 STC 10DH.1 STC 10DH.2 STC 10DH.3 CMP #0 BEQ LLL3 CMP #1 BEQ LLL2 CMP #2 BEQ LLL1 CMP #3 BEQ LLL0 CMP #4 BEQ LLL1 CMP #5 BEQ LLL2 CMP #6 BEQ LLL3 CMP #7 BEQ LLL4 LLL0: STC 10DH.1 LLL1: STC 10DH.2 LLL2: STC 10DH.3 LLL3: STC 10DH.0 LLL4: STC 111H.1 INC TEMPCNT IF [TEMPCNT]==#8 LDM TEMPCNT,#0 ENDIF RET ; ; ;************************************************************************** ; NOT_USED: nop ;Discard Unexpected Interrupts reti ; END ;Notice Program End
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